further generalize fpga/vlsi builds

2014-09-08 00:21:57 -07:00
parent 3175a40509
commit ddfd3ce968
8 changed files with 45 additions and 48 deletions
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@ -112,7 +112,7 @@ module rocketTestHarness;
  wire #0.1 mem_bk_in_valid_delay = mem_bk_in_valid;
  wire mem_bk_out_valid_delay; assign #0.1 mem_bk_out_valid = mem_bk_out_valid_delay;

-  `TOP dut
+  Top dut
  (
    .clk(clk),
    .reset(reset),