riscv/rocket-chip
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generate consts.vh from chisel source

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This commit is contained in:
Yunsup Lee
2014-09-10 17:14:55 -07:00
parent cfecd8832d
commit 02c08a156f
8 changed files with 23 additions and 27 deletions
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11
vsrc/backup_mem.v
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@ -1,4 +1,5 @@
`define ceilLog2(x) ((x) > 2**30 ? 31 : \
`define ceilLog2(x) ( \
(x) > 2**30 ? 31 : \
(x) > 2**29 ? 30 : \
(x) > 2**28 ? 29 : \
(x) > 2**27 ? 28 : \
@ -31,7 +32,7 @@
(x) > 2**0 ? 1 : 0)
`ifdef MEM_BACKUP_EN
module BRAMMem
module BackupMemory
(
input clk,
input reset,
@ -40,7 +41,7 @@ module BRAMMem
output mem_req_ready,
input mem_req_rw,
input [`MEM_ADDR_BITS-1:0] mem_req_addr,
input [15:0] mem_req_tag,
input [`MEM_TAG_BITS-1:0] mem_req_tag,
input mem_req_data_valid,
output mem_req_data_ready,
@ -48,14 +49,14 @@ module BRAMMem
output reg mem_resp_valid,
output reg [`MEM_DATA_BITS-1:0] mem_resp_data,
output reg [15:0] mem_resp_tag
output reg [`MEM_TAG_BITS-1:0] mem_resp_tag
);
localparam DATA_CYCLES = 4;
localparam DEPTH = 2*1024*1024;
reg [`ceilLog2(DATA_CYCLES)-1:0] cnt;
reg [15:0] tag;
reg [`MEM_TAG_BITS-1:0] tag;
reg state_busy, state_rw;
reg [`MEM_ADDR_BITS-1:0] addr;

8
vsrc/const.vh
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@ -1,8 +0,0 @@
`ifndef CONST_VH
`define CONST_VH
`define MEM_ADDR_BITS 34
`define MEM_DATA_BITS 128
`define MEM_TAG_BITS 10
`endif // CONST_VH

4
vsrc/rocketTestHarness.v
View File

@ -1,7 +1,5 @@
// Test harness for Rocket RISC-V Processor
`define HTIF_WIDTH 16
extern "A" void htif_init
(
input reg [31:0] htif_width,
@ -233,7 +231,7 @@ module rocketTestHarness;
.io_wide_resp_bits_tag(mem_bk_resp_tag)
);
BRAMMem mem
BackupMemory mem
(
.clk(htif_clk),
.reset(reset),