Howard Mao
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4b4e8f7f62
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fixes for priv-1.9 changes
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2016-05-02 18:25:02 -07:00 |
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Andrew Waterman
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7285f5e6bf
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Don't drive D$ kill/phys signals for SimpleHellaCacheIF
They don't do anything.
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2016-04-01 19:31:54 -07:00 |
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Palmer Dabbelt
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50f61687de
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Work around Chisel3's lack of 0-width wires
This is super ugly, but it's necessary to get Chisel3 to compile. Note
that this still fails simulations in Chisel3, so it might be wrong.
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2016-03-14 22:50:37 -07:00 |
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Howard Mao
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24eecee148
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add DMA test
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2015-12-16 21:26:22 -08:00 |
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Howard Mao
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158d1d870c
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do all the writes before doing the gets in GeneratorTest
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2015-11-21 09:42:00 -08:00 |
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Howard Mao
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640544ea5a
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generalize test harness
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2015-11-18 22:54:05 -08:00 |
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Howard Mao
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8bc90ab9bd
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separate out common functionality
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2015-11-18 20:53:19 -08:00 |
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Howard Mao
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10f4c6c71c
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interleave cached and uncached requests
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2015-11-12 11:34:44 -08:00 |
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Howard Mao
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f93872d6b4
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make sure cached generator actually drives finished signal
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2015-11-11 18:45:36 -08:00 |
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Howard Mao
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9482d944ca
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make Uncached generator vary the alloc bit
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2015-11-11 18:26:56 -08:00 |
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Howard Mao
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8a6b231b08
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explicitly configure the number of requests being sent by generators
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2015-11-11 14:32:19 -08:00 |
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Howard Mao
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13f62e0364
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make sure generators can detect lockup
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2015-11-10 14:39:56 -08:00 |
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Howard Mao
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d844bee310
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properly shift grant data when checking correctness
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2015-10-31 18:58:05 -07:00 |
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Howard Mao
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644b66a3a8
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selectively enable or disable uncached and cached generators
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2015-10-31 17:43:25 -07:00 |
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Howard Mao
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bcc631f756
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generate word-size requests in uncached generator
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2015-10-31 17:43:08 -07:00 |
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Howard Mao
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c1f42ce3d4
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add an L1 cache request generator
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2015-10-30 12:49:57 -07:00 |
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Howard Mao
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3103fa8da2
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rename tl to mem in generator
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2015-10-27 17:14:56 -07:00 |
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Howard Mao
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aeb9c86459
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use the uncached port instead of the cached port
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2015-10-26 23:09:36 -07:00 |
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Howard Mao
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b22088d934
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make sure data checked is same as data sent
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2015-10-26 21:55:04 -07:00 |
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Howard Mao
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2b252bc6ff
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first commit
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2015-10-26 21:43:50 -07:00 |
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