04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
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This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
3c95afebc6
Shift set index for multi-bank configurations
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Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
2b977325e3
Make prefetch type available in a_type, issue probeInvalidates for putPrefetches
2015-11-16 23:26:13 -08:00
0290635454
amo_shift_bits -> amo_shift_bytes
2015-11-16 19:07:58 -08:00
64aaf71b06
L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
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Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
2015-11-16 18:10:09 -08:00
03fa06e6e7
fix prefetch lockup on L2 hit
2015-11-15 12:51:34 -08:00
e12efab423
skip meta_write state if no meta write pending
2015-11-13 13:50:35 -08:00
7e7d688a01
make sure L2 passes no-alloc acquires through to outer memory
2015-11-12 15:40:58 -08:00
7733fbe6a3
make sure no-alloc write still updates data array if there is a cache hit
2015-11-12 11:39:36 -08:00
b59ce5fed4
make sure L2 waits for outer grant before sending grant for write request
2015-11-10 16:06:14 -08:00
e3efc09b5b
remove unnecessary UInt encode/decode on releaseMatches path
2015-11-05 17:20:03 -08:00
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
f8594da1d3
depend on external cde library
2015-10-21 18:17:17 -07:00
d391f97953
Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
2015-10-16 19:11:06 -07:00
7fa3eb95e3
refactor tilelink params
2015-10-14 12:13:37 -07:00
66ea39638e
GlobalAddrMap
2015-10-14 00:23:28 -07:00
31be6407ec
Removed all traces of params
2015-10-14 00:23:28 -07:00
3b1da4c57e
Revert "replace remaining uses of Vec.fill"
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This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
d1f2d40a90
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
350d530766
Use Vec.fill, not Vec.apply, for Vec literals
2015-08-27 10:00:43 -07:00
94287fed90
Avoid type-unsafe assignments
2015-08-27 09:57:36 -07:00
05d311c517
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
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The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
a69c749249
Fix compilation with scala 2.11.6
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We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
15cec0eab7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
b4e38192a1
Fix (?) L2$ miss bug
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The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
ea76800d1a
Fix data array reset bug
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io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
3cf1778c92
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
2015-04-06 12:22:23 -07:00
9708d25dff
Restructure L2 state machine and utilize HeaderlessTileLinkIO
2015-04-06 12:19:51 -07:00
ced627f00a
slight mod to pending_puts
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cleaner state transition logic
2015-04-01 15:24:53 -07:00
3cf033180f
pending read fix
2015-03-18 22:41:09 -07:00
