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Commit Graph

107 Commits

Author SHA1 Message Date
Edmond Cote
2489a08328 Header required for -DVM_TRACE=1 (#1294)
With -DVM_TRACE=1 on gcc 7.2.0.

Very small change.  May only affect me.  Is it possible -DVM_TRACE=1 is not regressed?

~~~~
http://en.cppreference.com/w/cpp/memory/unique_ptr
[..]/emulator.cc: In function ‘int main(int, char**)’:
[..]/emulator.cc:254:19: error: ‘VerilatedVcdFILE’ was not declared in this scope
   std::unique_ptr<VerilatedVcdFILE> vcdfd(new VerilatedVcdFILE(vcdfile));
~~~~
More info : http://en.cppreference.com/w/cpp/memory/unique_ptr

~~~~
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/x86_64-linux-gnu/7/lto-wrapper
OFFLOAD_TARGET_NAMES=nvptx-none
OFFLOAD_TARGET_DEFAULT=1
Target: x86_64-linux-gnu
Configured with: ../src/configure -v --with-pkgversion='Ubuntu 7.2.0-8ubuntu3.2' --with-bugurl=file:///usr/share/doc/gcc-7/README.Bugs --enable-languages=c,ada,c++,go,brig,d,fortran,objc,obj-c++ --prefix=/usr --with-gcc-major-version-only --program-suffix=-7 --program-prefix=x86_64-linux-gnu- --enable-shared --enable-linker-build-id --libexecdir=/usr/lib --without-included-gettext --enable-threads=posix --libdir=/usr/lib --enable-nls --with-sysroot=/ --enable-clocale=gnu --enable-libstdcxx-debug --enable-libstdcxx-time=yes --with-default-libstdcxx-abi=new --enable-gnu-unique-object --disable-vtable-verify --enable-libmpx --enable-plugin --enable-default-pie --with-system-zlib --with-target-system-zlib --enable-objc-gc=auto --enable-multiarch --disable-werror --with-arch-32=i686 --with-abi=m64 --with-multilib-list=m32,m64,mx32 --enable-multilib --with-tune=generic --enable-offload-targets=nvptx-none --without-cuda-driver --enable-checking=release --build=x86_64-linux-gnu --host=x86_64-linux-gnu --target=x86_64-linux-gnu
Thread model: posix
gcc version 7.2.0 (Ubuntu 7.2.0-8ubuntu3.2) 
~~~~
2018-03-19 20:07:28 -05:00
Megan Wachs
42e614550c JTAGVPI: remove it in favor of remote bitbang 2018-03-07 10:53:49 -08:00
Schuyler Eldridge
135f06cefc Clarify errors, init jtag error code to zero (#1241)
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-16 13:03:51 -08:00
Paul Rigge
ac62bf7f22 Use bind from global namespace 2018-02-09 14:16:20 -08:00
Schuyler Eldridge
355d3b15e8 Merge 'origin/master' into auto-plusargs 2018-01-16 15:45:53 -05:00
Schuyler Eldridge
e52d52ae99 Link PlusArg to emulator command line options
- adds a mutable singleton (PlusArgArtefacts) to store information
  about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
  consumed by emulator.cc for correct argument parsing and help text
  generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
  ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
Edmond Cote
ff11673a9c
remove string type ambiguity in header
I ran into a compilation issue.

This link explains the problem well: https://stackoverflow.com/a/5499222/3736700

For example, in a header file, it is generally not considered a good idea to put the line using namespace std; (or to use any namespace, for that matter) because it can cause names in files that include that header to become ambiguous. In this setup, you would just #include <string> in the header, then use std::string to refer to the string type.
2018-01-13 13:29:22 -08:00
Megan Wachs
427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs 2018-01-05 17:08:21 -08:00
Megan Wachs
e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
Megan Wachs
b643f3dca6 debug regressions: some whitespace and null ptr cleanup 2018-01-05 17:08:21 -08:00
Schuyler Eldridge
96dd5d8c38 Emulator example clarifications
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
7ae6bf7611 Arguments clarification, add examples
This clarifies and provides consistent for the command line arguments
usage text.

This adds a set of examples for running the rocket-chip emulator.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
1aa87f6578 Make emulator.cc understand HTIF arguments
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
3ead9a5d2d Move check on VCS inside riscv-fesvr
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
Megan Wachs
9df3604007 emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
Megan Wachs
024cd52c44 debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
Megan Wachs
e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
Megan Wachs
0493372027 jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
Wesley W. Terpstra
7f1d3c445f Plusargs -- tilelink timeout detection from the command line (#752)
* util: PlusArg gives Chisel access to the command-line

* tilelink2: add a progress watchdog to Monitors
2017-05-18 22:49:59 -07:00
Andrew Waterman
458d80cb18 For Verilator, rename +start to +dump-start to match VCS 2017-04-20 17:00:46 -07:00
Megan Wachs
9de06f8c83 Merge remote-tracking branch 'origin/master' into debug_v013_pr 2017-03-30 08:01:11 -07:00
Schuyler Eldridge
c61714a465 Pass MODEL variable to emulator.cc
This enables hot-swapping of the top-level test harness by specifying
`MODEL=MyTestHarness` when building the emulator.
2017-03-30 02:08:01 -07:00
Megan Wachs
ca9a5a1cf7 debug: Fixes in how the SimDTM was hooked up to FESVR 2017-03-28 21:13:45 -07:00
Minux Ma
622e311962 Fix emulator argument processing for unknown DTM arguments (#498)
Revision 7e79421 (issue #484) makes emulator.cc rejecting any unrecognized
+arg "legacy" arguments, however, this breaks riscv-torture emulator tests
as it needs to pass +signature to the DTM.

I think it is actually impossible to check for unknown argument here
unless we hardcode a list of all arguments recognized by fesrv. Fix this
issue by passing all arguments starting with the first unknown argument
to DTM.

Updates #484.

Signed-off-by: Minux Ma <minux.ma@gmail.com>
2017-01-16 13:42:45 -08:00
Schuyler Eldridge
7e794212d9 Cleanup emulator.cc, use getopt, add help text (#487)
This changes the emulator to conform to POSIX-style options (e.g.,
short/'-' and long/'--') while preserving legacy option parsing (i.e.,
'+'). Options are read from the user until the first
non-option (either POSIX or legacy) is encountered. This and
everything following is assumed to be the binary and any arguments the
user wants to run on the emulator. All non-options are passed directly
to the DTM. This allows for the same option to be passed, safely, to
both the emulator and the binary, e.g., "+verbose".

This introduces a dependency on <getopt.h>.

Closes #484.
2016-12-13 14:29:57 -08:00
Wesley W. Terpstra
b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Richard Xia
183ae58704 Use a random port number for JTAG VPI. 2016-10-26 11:40:45 -07:00
Andrew Waterman
6472d4c245 Print Verilator random seed when +verbose is passed 2016-10-04 22:29:39 -07:00
Andrew Waterman
2ab61f1a71 Chisel implicit clock is now named clock, not clk 2016-09-21 16:16:47 -07:00
Henry Cook
9e2b0aad65 Revert "allow MODEL to be something other than TestHarness"
This reverts commit bf253aaa97.
2016-09-15 11:53:05 -07:00
Howard Mao
bf253aaa97 allow MODEL to be something other than TestHarness 2016-09-14 20:51:56 -07:00
Scott Beamer
cd12fd1cbb fix clang support for emulator-debug 2016-09-14 12:20:37 -07:00
Colin Schmidt
cf3c6fa277 add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00
Andrew Waterman
2dfcf18167 Filter simv command-line args starting with -cm
These confuse HTIF, so don't pass them through.

Contributed by @scottj97.
2016-08-31 13:39:35 -07:00
Megan Wachs
dd4a50c452 Add JTAG DTM and test support in simulation
Initial cut

checkpoint which compiles and runs but there is some off-by-1 in the protocol

Debugging the clock crossing logic

checkpoint which works

Clean up the AsyncMailbox black box
2016-08-19 16:08:17 -07:00
Howard Mao
35fbbfc70d put test harness on the heap in emulator 2016-08-16 14:50:40 -07:00
Andrew Waterman
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
Howard Mao
b64998ec05 make sure dramsim reads and writes occur in the order they are received 2016-07-11 18:11:00 -07:00
Andrew Waterman
9751ea0f35 Fix Verilator VCD (#157) 2016-07-09 02:37:39 -07:00
Andrew Waterman
87a4858aa6 Exit from testbench, not C code
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Andrew Waterman
4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
50e3caef36 get rid of Zscale file I missed last time 2016-05-31 14:33:38 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00