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rocket-chip/csrc
Schuyler Eldridge 3ead9a5d2d Move check on VCS inside riscv-fesvr
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
..
comlog.cc copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
emulator.cc emulator: No reason not to emit waveforms during reset 2018-01-05 17:08:21 -08:00
float_fix.cc copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
jtag_vpi.c jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners 2017-05-26 11:48:45 -07:00
remote_bitbang.cc debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved 2018-01-05 17:08:21 -08:00
remote_bitbang.h Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 2018-01-05 16:02:52 -08:00
SimDTM.cc Move check on VCS inside riscv-fesvr 2018-01-05 17:08:21 -08:00
SimJTAG.cc Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 2018-01-05 16:02:52 -08:00
verilator.h add STOP_COND to emulator & match vsim PRINTF_COND 2016-09-09 11:07:17 -07:00