riscv/rocket-chip
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Remove HTIF; use debug module for testing in simulation

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This commit is contained in:
Andrew Waterman
2016-06-23 00:17:29 -07:00
parent 255ef05e21
commit 30331fcaeb
12 changed files with 198 additions and 387 deletions
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173
csrc/emulator.cc
View File

@ -1,6 +1,5 @@
// See LICENSE for license details.
#include "htif_emulator.h"
#ifndef VERILATOR
#include "emulator.h"
#else
@ -11,6 +10,7 @@
#endif
#include "mm.h"
#include "mm_dramsim2.h"
#include <fesvr/dtm.h>
#include <iostream>
#include <fcntl.h>
#include <signal.h>
@ -24,12 +24,12 @@
#include "emulator_type.h"
htif_emulator_t* htif;
static dtm_t* dtm;
bool verbose;
void handle_sigterm(int sig)
{
htif->stop();
dtm->stop();
}
int main(int argc, char** argv)
@ -126,34 +126,24 @@ int main(int argc, char** argv)
load_mem(mems, loadmem, CACHE_BLOCK_BYTES, N_MEM_CHANNELS);
}
// Instantiate HTIF
htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
assert(HTIF_WIDTH % 8 == 0 && HTIF_WIDTH <= 8*sizeof(uint64_t));
dtm = new dtm_t(std::vector<std::string>(argv + 1, argv + argc));
signal(SIGTERM, handle_sigterm);
// reset for one host_clk cycle to handle pipelined reset
// reset for several cycles to handle pipelined reset
for (int i = 0; i < 10; i++) {
#ifndef VERILATOR
tile.Top__io_host_in_valid = LIT<1>(0);
tile.Top__io_host_out_ready = LIT<1>(0);
for (int i = 0; i < 3; i += tile.Top__io_host_clk_edge.to_bool())
{
tile.clock_lo(LIT<1>(1));
tile.clock_hi(LIT<1>(1));
}
#else
tile.io_host_in_valid = 0;
tile.io_host_out_ready = 0;
for (int i = 0; i < 3; i += tile.io_host_clk_edge)
{
tile.reset = 1;
tile.clk = 0;
tile.eval();
tile.clk = 1;
tile.eval();
}
tile.reset = 0;
tile.reset = 0;
#endif
}
bool_t *mem_ar_valid[N_MEM_CHANNELS];
bool_t *mem_ar_ready[N_MEM_CHANNELS];
@ -189,42 +179,31 @@ int main(int argc, char** argv)
#include TBFRAG
while (!htif->done() && (trace_count >> 1) < max_cycles && ret == 0)
while (!dtm->done() && (trace_count >> 1) < max_cycles && ret == 0)
{
for (int i = 0; i < N_MEM_CHANNELS; i++) {
#ifndef VERILATOR
*mem_ar_ready[i] = LIT<1>(mm[i]->ar_ready());
*mem_aw_ready[i] = LIT<1>(mm[i]->aw_ready());
*mem_w_ready[i] = LIT<1>(mm[i]->w_ready());
value(mem_ar_ready[i]) = mm[i]->ar_ready();
value(mem_aw_ready[i]) = mm[i]->aw_ready();
value(mem_w_ready[i]) = mm[i]->w_ready();
*mem_b_valid[i] = LIT<1>(mm[i]->b_valid());
*mem_b_bits_resp[i] = LIT<64>(mm[i]->b_resp());
*mem_b_bits_id[i] = LIT<64>(mm[i]->b_id());
value(mem_b_valid[i]) = mm[i]->b_valid();
value(mem_b_bits_resp[i]) = mm[i]->b_resp();
value(mem_b_bits_id[i]) = mm[i]->b_id();
*mem_r_valid[i] = LIT<1>(mm[i]->r_valid());
*mem_r_bits_resp[i] = LIT<64>(mm[i]->r_resp());
*mem_r_bits_id[i] = LIT<64>(mm[i]->r_id());
*mem_r_bits_last[i] = LIT<1>(mm[i]->r_last());
value(mem_r_valid[i]) = mm[i]->r_valid();
value(mem_r_bits_resp[i]) = mm[i]->r_resp();
value(mem_r_bits_id[i]) = mm[i]->r_id();
value(mem_r_bits_last[i]) = mm[i]->r_last();
memcpy(mem_r_bits_data[i]->values, mm[i]->r_data(), mem_width);
#else
*mem_ar_ready[i] = mm[i]->ar_ready();
*mem_aw_ready[i] = mm[i]->aw_ready();
*mem_w_ready[i] = mm[i]->w_ready();
*mem_b_valid[i] = mm[i]->b_valid();
*mem_b_bits_resp[i] = mm[i]->b_resp();
*mem_b_bits_id[i] = mm[i]->b_id();
*mem_r_valid[i] = mm[i]->r_valid();
*mem_r_bits_resp[i] = mm[i]->r_resp();
*mem_r_bits_id[i] = mm[i]->r_id();
*mem_r_bits_last[i] = mm[i]->r_last();
memcpy(mem_r_bits_data[i], mm[i]->r_data(), mem_width);
#endif
memcpy(values(mem_r_bits_data[i]), mm[i]->r_data(), mem_width);
}
value(field(io_debug_resp_ready)) = dtm->resp_ready();
value(field(io_debug_req_valid)) = dtm->req_valid();
value(field(io_debug_req_bits_addr)) = dtm->req_bits().addr;
value(field(io_debug_req_bits_op)) = dtm->req_bits().op;
value(field(io_debug_req_bits_data)) = dtm->req_bits().data;
try {
#ifndef VERILATOR
tile.clock_lo(LIT<1>(0));
@ -244,67 +223,41 @@ int main(int argc, char** argv)
std::cerr << e.what() << std::endl;
}
dtm_t::resp debug_resp_bits;
debug_resp_bits.resp = value(field(io_debug_resp_bits_resp));
debug_resp_bits.data = value(field(io_debug_resp_bits_data));
dtm->tick(
value(field(io_debug_req_ready)),
value(field(io_debug_resp_valid)),
debug_resp_bits
);
for (int i = 0; i < N_MEM_CHANNELS; i++) {
mm[i]->tick(
#ifndef VERILATOR
mem_ar_valid[i]->to_bool(),
mem_ar_bits_addr[i]->lo_word() - MEM_BASE,
mem_ar_bits_id[i]->lo_word(),
mem_ar_bits_size[i]->lo_word(),
mem_ar_bits_len[i]->lo_word(),
value(mem_ar_valid[i]),
value(mem_ar_bits_addr[i]) - MEM_BASE,
value(mem_ar_bits_id[i]),
value(mem_ar_bits_size[i]),
value(mem_ar_bits_len[i]),
mem_aw_valid[i]->to_bool(),
mem_aw_bits_addr[i]->lo_word() - MEM_BASE,
mem_aw_bits_id[i]->lo_word(),
mem_aw_bits_size[i]->lo_word(),
mem_aw_bits_len[i]->lo_word(),
value(mem_aw_valid[i]),
value(mem_aw_bits_addr[i]) - MEM_BASE,
value(mem_aw_bits_id[i]),
value(mem_aw_bits_size[i]),
value(mem_aw_bits_len[i]),
mem_w_valid[i]->to_bool(),
mem_w_bits_strb[i]->lo_word(),
mem_w_bits_data[i]->values,
mem_w_bits_last[i]->to_bool(),
value(mem_w_valid[i]),
value(mem_w_bits_strb[i]),
values(mem_w_bits_data[i]),
value(mem_w_bits_last[i]),
mem_r_ready[i]->to_bool(),
mem_b_ready[i]->to_bool()
#else
*mem_ar_valid[i],
*mem_ar_bits_addr[i] - MEM_BASE,
*mem_ar_bits_id[i],
*mem_ar_bits_size[i],
*mem_ar_bits_len[i],
*mem_aw_valid[i],
*mem_aw_bits_addr[i] - MEM_BASE,
*mem_aw_bits_id[i],
*mem_aw_bits_size[i],
*mem_aw_bits_len[i],
*mem_w_valid[i],
*mem_w_bits_strb[i],
mem_w_bits_data[i],
*mem_w_bits_last[i],
*mem_r_ready[i],
*mem_b_ready[i]
#endif
value(mem_r_ready[i]),
value(mem_b_ready[i])
);
}
#ifndef VERILATOR
if (tile.Top__io_host_clk_edge.to_bool())
{
static bool htif_in_valid = false;
static val_t htif_in_bits;
if (tile.Top__io_host_in_ready.to_bool() || !htif_in_valid)
htif_in_valid = htif->recv_nonblocking(&htif_in_bits, HTIF_WIDTH/8);
tile.Top__io_host_in_valid = LIT<1>(htif_in_valid);
tile.Top__io_host_in_bits = LIT<64>(htif_in_bits);
if (tile.Top__io_host_out_valid.to_bool())
htif->send(tile.Top__io_host_out_bits.values, HTIF_WIDTH/8);
tile.Top__io_host_out_ready = LIT<1>(1);
}
if (verbose && (trace_count >> 1) >= start)
tile.print(stderr);
@ -314,20 +267,6 @@ int main(int argc, char** argv)
tile.clock_hi(LIT<1>(0));
#else
if (tile.io_host_clk_edge)
{
static bool htif_in_valid = false;
static uint64_t htif_in_bits;
if (tile.io_host_in_ready || !htif_in_valid)
htif_in_valid = htif->recv_nonblocking(&htif_in_bits, HTIF_WIDTH/8);
tile.io_host_in_valid = htif_in_valid;
tile.io_host_in_bits = htif_in_bits;
if (tile.io_host_out_valid)
htif->send(&tile.io_host_out_bits, HTIF_WIDTH/8);
tile.io_host_out_ready = 1;
}
tile.clk = 1;
tile.eval();
#if VM_TRACE
@ -347,10 +286,10 @@ int main(int argc, char** argv)
#endif
#endif
if (htif->exit_code())
if (dtm->exit_code())
{
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", htif->exit_code(), random_seed, trace_count >> 1);
ret = htif->exit_code();
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count >> 1);
ret = dtm->exit_code();
}
else if ((trace_count >> 1) == max_cycles)
{
@ -362,7 +301,7 @@ int main(int argc, char** argv)
fprintf(stderr, "Completed after %ld cycles\n", trace_count >> 1);
}
delete htif;
delete dtm;
return ret;
}

9
csrc/emulator_type.h
View File

@ -1,10 +1,15 @@
// See LICENSE for license details.
#ifndef VERILATOR
#define bool_t dat_t<1>
# define bool_t dat_t<1>
# define values(x) ((x)->values)
# define field(name) &(tile.Top__ ## name)
#else
#define bool_t CData
# define bool_t CData
# define values(x) (x)
# define field(name) &(tile.name)
#endif
#define value(x) (*values(x))
#ifndef VERILATOR
#define mem_addr_t dat_t<MEM_ADDR_BITS>

69
csrc/vcs_main.rocketTestHarness.cc
View File

@ -1,8 +1,9 @@
// See LICENSE for license details.
#include "htif_emulator.h"
#include "mm.h"
#include "mm_dramsim2.h"
#include <fesvr/dtm.h>
#include <assert.h>
#include <DirectC.h>
#include <stdio.h>
#include <stdlib.h>
@ -14,17 +15,14 @@ extern "C" {
extern int vcs_main(int argc, char** argv);
static htif_emulator_t* htif;
static unsigned htif_bytes = HTIF_WIDTH / 8;
static dtm_t* dtm;
static mm_t* mm[N_MEM_CHANNELS];
static const char* loadmem;
static bool dramsim = false;
static int memory_channel_mux_select = 0;
void htif_fini(vc_handle failure)
void do_exit(vc_handle failure)
{
delete htif;
htif = NULL;
exit(vc_getScalar(failure));
}
@ -40,7 +38,7 @@ int main(int argc, char** argv)
memory_channel_mux_select = atoi(argv[i]+27);
}
htif = new htif_emulator_t(std::vector<std::string>(argv + 1, argv + argc));
dtm = new dtm_t(std::vector<std::string>(argv + 1, argv + argc));
for (int i=0; i<N_MEM_CHANNELS; i++) {
mm[i] = dramsim ? (mm_t*)(new mm_dramsim2_t) : (mm_t*)(new mm_magic_t);
@ -172,36 +170,45 @@ void memory_tick(
vc_put4stVector(r_data, d);
}
void htif_tick
void debug_tick
(
vc_handle htif_in_valid,
vc_handle htif_in_ready,
vc_handle htif_in_bits,
vc_handle htif_out_valid,
vc_handle htif_out_ready,
vc_handle htif_out_bits,
vc_handle debug_req_valid,
vc_handle debug_req_ready,
vc_handle debug_req_bits_addr,
vc_handle debug_req_bits_op,
vc_handle debug_req_bits_data,
vc_handle debug_resp_valid,
vc_handle debug_resp_ready,
vc_handle debug_resp_bits_resp,
vc_handle debug_resp_bits_data,
vc_handle exit
)
{
static bool peek_in_valid;
static uint32_t peek_in_bits;
if (vc_getScalar(htif_in_ready))
peek_in_valid = htif->recv_nonblocking(&peek_in_bits, htif_bytes);
vec32 tmp[2];
dtm_t::resp resp_bits;
vc_get4stVector(debug_resp_bits_resp, tmp);
resp_bits.resp = tmp[0].d;
vc_get4stVector(debug_resp_bits_data, tmp);
resp_bits.data = tmp[0].d | ((uint64_t)tmp[1].d << 32);
vc_putScalar(htif_out_ready, 1);
if (vc_getScalar(htif_out_valid))
{
vec32* bits = vc_4stVectorRef(htif_out_bits);
htif->send(&bits->d, htif_bytes);
}
dtm->tick
(
vc_getScalar(debug_req_ready),
vc_getScalar(debug_resp_valid),
resp_bits
);
vec32 bits = {0, 0};
bits.d = peek_in_bits;
vc_put4stVector(htif_in_bits, &bits);
vc_putScalar(htif_in_valid, peek_in_valid);
bits.d = htif->done() ? (htif->exit_code() << 1 | 1) : 0;
vc_put4stVector(exit, &bits);
vc_putScalar(debug_resp_ready, dtm->resp_ready());
vc_putScalar(debug_req_valid, dtm->req_valid());
tmp[0].d = dtm->req_bits().addr;
vc_put4stVector(debug_req_bits_addr, tmp);
tmp[0].d = dtm->req_bits().op;
vc_put4stVector(debug_req_bits_op, tmp);
tmp[0].d = dtm->req_bits().data;
tmp[1].d = dtm->req_bits().data >> 32;
vc_put4stVector(debug_req_bits_data, tmp);
tmp[0].d = dtm->done() ? (dtm->exit_code() << 1 | 1) : 0;
vc_put4stVector(exit, tmp);
}
}