allow MODEL to be something other than TestHarness

2016-09-14 20:04:33 -07:00
parent 8550582f84
commit bf253aaa97
4 changed files with 4 additions and 3 deletions
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@ -65,7 +65,7 @@ int main(int argc, char** argv)
  srand48(random_seed);

  Verilated::randReset(2);
-  VTestHarness *tile = new VTestHarness;
+  MODEL *tile = new MODEL;

 #if VM_TRACE
  Verilated::traceEverOn(true); // Verilator must compute traced signals