Megan Wachs 427b6c9ab8 Emulator: Update it to allow some hard-coded Verilog PlusArgs

2018-01-05 17:08:21 -08:00

..

comlog.cc

copyright: ran scripts/modify-copyright

2016-11-27 22:15:43 -08:00

emulator.cc

Emulator: Update it to allow some hard-coded Verilog PlusArgs

2018-01-05 17:08:21 -08:00

float_fix.cc

copyright: ran scripts/modify-copyright

2016-11-27 22:15:43 -08:00

jtag_vpi.c

jtag_vpi: Attempt to more aggressively flush the simulator output as it is needed by other listeners

2017-05-26 11:48:45 -07:00

remote_bitbang.cc

Debug regressions: use a plusarg to enable remote bitbang.

2018-01-05 17:08:21 -08:00

remote_bitbang.h

Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.

2018-01-05 16:02:52 -08:00

SimDTM.cc

Move check on VCS inside riscv-fesvr

2018-01-05 17:08:21 -08:00

SimJTAG.cc

debug regressions: some whitespace and null ptr cleanup

2018-01-05 17:08:21 -08:00

verilator.h

add STOP_COND to emulator & match vsim PRINTF_COND

2016-09-09 11:07:17 -07:00