1
0
rocket-chip/rocket/src/main/scala/csr.scala

247 lines
8.4 KiB
Scala
Raw Normal View History

package rocket
2012-10-08 05:15:54 +02:00
import Chisel._
import Util._
2012-10-08 05:15:54 +02:00
import Node._
2013-11-08 00:42:03 +01:00
import uncore.HTIFIO
import uncore.AddressSpaceConfiguration
2012-10-08 05:15:54 +02:00
import scala.math._
2012-11-27 10:28:06 +01:00
class Status extends Bundle {
val ip = Bits(width = 8)
2012-11-27 10:28:06 +01:00
val im = Bits(width = 8)
val zero = Bits(width = 7)
val er = Bool()
2012-11-27 10:28:06 +01:00
val vm = Bool()
val s64 = Bool()
val u64 = Bool()
val ef = Bool()
2013-08-24 06:16:28 +02:00
val pei = Bool()
val ei = Bool()
val ps = Bool()
val s = Bool()
2012-11-27 10:28:06 +01:00
}
2013-11-25 13:35:15 +01:00
object CSR
{
2012-11-27 10:28:06 +01:00
// commands
2013-11-25 13:35:15 +01:00
val SZ = 2
val X = Bits("b??", 2)
val N = Bits(0,2)
val W = Bits(1,2)
val S = Bits(2,2)
val C = Bits(3,2)
}
2014-05-10 04:26:43 +02:00
class CSRFileIO(implicit conf: RocketConfiguration) extends Bundle {
val host = new HTIFIO(conf.tl.ln.nClients)
val rw = new Bundle {
val addr = UInt(INPUT, 12)
val cmd = Bits(INPUT, CSR.SZ)
val rdata = Bits(OUTPUT, conf.xprlen)
val wdata = Bits(INPUT, conf.xprlen)
}
val status = new Status().asOutput
val ptbr = UInt(OUTPUT, conf.as.paddrBits)
val evec = UInt(OUTPUT, conf.as.vaddrBits+1)
val exception = Bool(INPUT)
val retire = UInt(INPUT, log2Up(1+conf.retireWidth))
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+conf.retireWidth)))
val cause = UInt(INPUT, conf.xprlen)
val badvaddr_wen = Bool(INPUT)
val pc = UInt(INPUT, conf.as.vaddrBits+1)
val sret = Bool(INPUT)
val fatc = Bool(OUTPUT)
val replay = Bool(OUTPUT)
val time = UInt(OUTPUT, conf.xprlen)
val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
val rocc = new RoCCInterface().flip
}
2013-11-25 13:35:15 +01:00
class CSRFile(implicit conf: RocketConfiguration) extends Module
{
2014-05-10 04:26:43 +02:00
val io = new CSRFileIO
2012-11-27 10:28:06 +01:00
val reg_epc = Reg(Bits(width = conf.as.vaddrBits+1))
val reg_badvaddr = Reg(Bits(width = conf.as.vaddrBits))
val reg_evec = Reg(Bits(width = conf.as.vaddrBits))
2013-08-12 19:39:11 +02:00
val reg_compare = Reg(Bits(width = 32))
2014-01-25 00:56:01 +01:00
val reg_cause = Reg(Bits(width = conf.xprlen))
2013-08-16 00:28:15 +02:00
val reg_tohost = Reg(init=Bits(0, conf.xprlen))
val reg_fromhost = Reg(init=Bits(0, conf.xprlen))
2013-08-24 06:16:28 +02:00
val reg_sup0 = Reg(Bits(width = conf.xprlen))
val reg_sup1 = Reg(Bits(width = conf.xprlen))
val reg_ptbr = Reg(UInt(width = conf.as.paddrBits))
2013-08-16 00:28:15 +02:00
val reg_stats = Reg(init=Bool(false))
2013-08-12 19:39:11 +02:00
val reg_status = Reg(new Status) // reset down below
2014-01-25 00:56:01 +01:00
val reg_time = WideCounter(conf.xprlen)
val reg_instret = WideCounter(conf.xprlen, io.retire)
2014-02-06 09:13:02 +01:00
val reg_uarch_counters = io.uarch_counters.map(WideCounter(conf.xprlen, _))
2013-11-25 13:35:15 +01:00
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
2012-11-27 10:28:06 +01:00
2013-08-16 00:28:15 +02:00
val r_irq_timer = Reg(init=Bool(false))
val r_irq_ipi = Reg(init=Bool(true))
val irq_rocc = Bool(!conf.rocc.isEmpty) && io.rocc.interrupt
2013-11-25 13:35:15 +01:00
val cpu_req_valid = io.rw.cmd != CSR.N
2013-08-12 19:39:11 +02:00
val host_pcr_req_valid = Reg(Bool()) // don't reset
2013-11-25 13:35:15 +01:00
val host_pcr_req_fire = host_pcr_req_valid && !cpu_req_valid
2013-08-12 19:39:11 +02:00
val host_pcr_rep_valid = Reg(Bool()) // don't reset
val host_pcr_bits = Reg(io.host.pcr_req.bits)
2012-12-06 23:22:07 +01:00
io.host.pcr_req.ready := !host_pcr_req_valid && !host_pcr_rep_valid
io.host.pcr_rep.valid := host_pcr_rep_valid
io.host.pcr_rep.bits := host_pcr_bits.data
when (io.host.pcr_req.fire()) {
host_pcr_req_valid := true
host_pcr_bits := io.host.pcr_req.bits
}
when (host_pcr_req_fire) {
host_pcr_req_valid := false
host_pcr_rep_valid := true
host_pcr_bits.data := io.rw.rdata
2012-12-06 23:22:07 +01:00
}
when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
2013-11-25 13:35:15 +01:00
val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
val decoded_addr = {
val map = for ((v, i) <- CSRs.all.zipWithIndex)
yield v -> UInt(BigInt(1) << i)
val out = ROM(map)(addr)
2013-11-25 13:35:15 +01:00
val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
for (i <- 0 until CSRs.all.size)
a(CSRs.all(i)) = out(i)
2013-11-25 13:35:15 +01:00
a
}
val wen = cpu_req_valid || host_pcr_req_fire && host_pcr_bits.rw
val wdata = Mux(cpu_req_valid, io.rw.wdata, host_pcr_bits.data)
2012-11-27 10:28:06 +01:00
io.status := reg_status
io.status.ip := Cat(r_irq_timer, reg_fromhost.orR, r_irq_ipi, Bool(false),
Bool(false), irq_rocc, Bool(false), Bool(false))
2013-11-25 13:35:15 +01:00
io.fatc := wen && decoded_addr(CSRs.fatc)
2013-08-24 06:16:28 +02:00
io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
2012-11-27 10:28:06 +01:00
io.ptbr := reg_ptbr
when (io.badvaddr_wen) {
val wdata = io.rw.wdata
val (upper, lower) = Split(wdata, conf.as.vaddrBits)
2013-08-12 19:39:11 +02:00
val sign = Mux(lower.toSInt < SInt(0), upper.andR, upper.orR)
reg_badvaddr := Cat(sign, lower).toSInt
2012-03-14 22:15:28 +01:00
}
2012-02-12 02:20:33 +01:00
when (io.exception) {
reg_status.s := true
reg_status.ps := reg_status.s
2013-08-24 06:16:28 +02:00
reg_status.ei := false
reg_status.pei := reg_status.ei
2013-08-12 19:39:11 +02:00
reg_epc := io.pc.toSInt
reg_cause := io.cause
}
2011-11-14 22:48:49 +01:00
2013-11-25 13:35:15 +01:00
when (io.sret) {
2012-11-27 10:28:06 +01:00
reg_status.s := reg_status.ps
2013-08-24 06:16:28 +02:00
reg_status.ei := reg_status.pei
}
2012-02-12 02:20:33 +01:00
2013-11-25 13:35:15 +01:00
when (reg_time(reg_compare.getWidth-1,0) === reg_compare) {
r_irq_timer := true
2011-11-13 09:27:57 +01:00
}
2012-02-12 02:20:33 +01:00
2013-11-25 13:35:15 +01:00
io.time := reg_time
io.host.ipi_req.valid := cpu_req_valid && decoded_addr(CSRs.send_ipi)
io.host.ipi_req.bits := io.rw.wdata
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
2013-11-25 13:35:15 +01:00
when (host_pcr_req_fire && !host_pcr_bits.rw && decoded_addr(CSRs.tohost)) { reg_tohost := UInt(0) }
2012-11-27 10:28:06 +01:00
val read_impl = Bits(2)
val read_ptbr = reg_ptbr(conf.as.paddrBits-1, conf.as.pgIdxBits) << conf.as.pgIdxBits
2013-11-25 13:35:15 +01:00
val read_mapping = collection.mutable.LinkedHashMap[Int,Bits](
CSRs.fflags -> (if (!params(HasFPU)) reg_fflags else UInt(0)),
CSRs.frm -> (if (!params(HasFPU)) reg_frm else UInt(0)),
CSRs.fcsr -> (if (!params(HasFPU)) Cat(reg_frm, reg_fflags) else UInt(0)),
2013-11-25 13:35:15 +01:00
CSRs.cycle -> reg_time,
CSRs.time -> reg_time,
CSRs.instret -> reg_instret,
CSRs.sup0 -> reg_sup0,
CSRs.sup1 -> reg_sup1,
CSRs.epc -> reg_epc,
CSRs.badvaddr -> reg_badvaddr,
CSRs.ptbr -> read_ptbr,
CSRs.asid -> UInt(0),
CSRs.count -> reg_time,
CSRs.compare -> reg_compare,
CSRs.evec -> reg_evec,
2014-01-25 00:56:01 +01:00
CSRs.cause -> reg_cause,
2013-11-25 13:35:15 +01:00
CSRs.status -> io.status.toBits,
CSRs.hartid -> io.host.id,
CSRs.impl -> read_impl,
CSRs.fatc -> read_impl, // don't care
CSRs.send_ipi -> read_impl, // don't care
CSRs.clear_ipi -> read_impl, // don't care
CSRs.stats -> reg_stats,
CSRs.tohost -> reg_tohost,
CSRs.fromhost -> reg_fromhost)
2014-02-06 09:13:02 +01:00
for (i <- 0 until reg_uarch_counters.size)
read_mapping += (CSRs.uarch0 + i) -> reg_uarch_counters(i)
io.rw.rdata := Mux1H(for ((k, v) <- read_mapping) yield decoded_addr(k) -> v)
2013-11-25 13:35:15 +01:00
io.fcsr_rm := reg_frm
when (io.fcsr_flags.valid) {
reg_fflags := reg_fflags | io.fcsr_flags.bits
}
2011-11-13 09:27:57 +01:00
when (wen) {
2013-11-25 13:35:15 +01:00
when (decoded_addr(CSRs.status)) {
reg_status := new Status().fromBits(wdata)
2013-08-24 06:16:28 +02:00
reg_status.s64 := true
reg_status.u64 := true
2012-11-27 10:28:06 +01:00
reg_status.zero := 0
2013-09-24 22:58:23 +02:00
if (!conf.vm) reg_status.vm := false
if (conf.rocc.isEmpty) reg_status.er := false
if (params(HasFPU)) reg_status.ef := false
2012-02-12 02:20:33 +01:00
}
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (decoded_addr(CSRs.epc)) { reg_epc := wdata(conf.as.vaddrBits,0).toSInt }
when (decoded_addr(CSRs.evec)) { reg_evec := wdata(conf.as.vaddrBits-1,0).toSInt }
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(conf.as.paddrBits-1, conf.as.pgIdxBits), Bits(0, conf.as.pgIdxBits)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
2012-02-12 02:20:33 +01:00
}
io.host.ipi_rep.ready := Bool(true)
when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
2013-08-13 05:51:54 +02:00
when(this.reset) {
2013-08-24 06:16:28 +02:00
reg_status.ei := false
reg_status.pei := false
2012-11-27 10:28:06 +01:00
reg_status.ef := false
reg_status.er := false
2012-11-27 10:28:06 +01:00
reg_status.ps := false
reg_status.s := true
reg_status.u64 := true
reg_status.s64 := true
reg_status.vm := false
reg_status.zero := 0
reg_status.im := 0
reg_status.ip := 0
}
}