1
0
rocket-chip/rocket/src/main/scala/dpath_util.scala

265 lines
9.2 KiB
Scala
Raw Normal View History

package rocket
2011-11-09 23:52:17 +01:00
import Chisel._;
import Node._;
import Constants._;
import scala.math._;
class ioDpathBTB extends Bundle()
{
2012-07-13 03:12:49 +02:00
val current_pc = UFix(INPUT, VADDR_BITS);
val hit = Bool(OUTPUT);
2012-07-13 03:12:49 +02:00
val target = UFix(OUTPUT, VADDR_BITS);
val wen = Bool(INPUT);
val clr = Bool(INPUT);
val invalidate = Bool(INPUT);
2012-07-13 03:12:49 +02:00
val correct_pc = UFix(INPUT, VADDR_BITS);
val correct_target = UFix(INPUT, VADDR_BITS);
}
// fully-associative branch target buffer
class rocketDpathBTB(entries: Int) extends Component
{
val io = new ioDpathBTB();
val repl_way = LFSR16(io.wen)(log2Up(entries)-1,0) // TODO: pseudo-LRU
var hit_reduction = Bool(false)
2012-05-24 19:33:15 +02:00
val hit = Bool()
val update = Bool()
var update_reduction = Bool(false)
val mux = (new Mux1H(entries)) { Bits(width = VADDR_BITS) }
for (i <- 0 until entries) {
val tag = Reg() { UFix() }
val target = Reg() { UFix() }
val valid = Reg(resetVal = Bool(false))
val my_hit = valid && tag === io.current_pc
val my_update = valid && tag === io.correct_pc
val my_clr = io.clr && my_update || io.invalidate
val my_wen = io.wen && (my_update || !update && UFix(i) === repl_way)
2012-02-12 02:20:33 +01:00
valid := !my_clr && (valid || my_wen)
when (my_wen) {
2012-02-12 02:20:33 +01:00
tag := io.correct_pc
target := io.correct_target
}
hit_reduction = hit_reduction || my_hit
update_reduction = update_reduction || my_update
mux.io.sel(i) := my_hit
mux.io.in(i) := target
}
hit := hit_reduction
update := update_reduction
io.hit := hit
io.target := mux.io.out.toUFix
}
class ioDpathPCR extends Bundle()
{
val host = new ioHTIF()
val r = new ioReadPort();
val w = new ioWritePort();
2012-07-13 03:12:49 +02:00
val status = Bits(OUTPUT, 32);
val ptbr = UFix(OUTPUT, PADDR_BITS);
val evec = UFix(OUTPUT, VADDR_BITS);
val exception = Bool(INPUT);
2012-07-13 03:12:49 +02:00
val cause = UFix(INPUT, 6);
val badvaddr_wen = Bool(INPUT);
2012-07-13 03:12:49 +02:00
val vec_irq_aux = Bits(INPUT, 64)
2012-03-14 22:15:28 +01:00
val vec_irq_aux_wen = Bool(INPUT)
2012-07-13 03:12:49 +02:00
val pc = UFix(INPUT, VADDR_BITS+1);
2012-02-12 02:20:33 +01:00
val eret = Bool(INPUT);
val ei = Bool(INPUT);
val di = Bool(INPUT);
val ptbr_wen = Bool(OUTPUT);
val irq_timer = Bool(OUTPUT);
val irq_ipi = Bool(OUTPUT);
2012-07-18 07:52:53 +02:00
val replay = Bool(OUTPUT)
2012-07-13 03:12:49 +02:00
val vecbank = Bits(OUTPUT, 8)
val vecbankcnt = UFix(OUTPUT, 4)
val vec_appvl = UFix(INPUT, 12)
val vec_nxregs = UFix(INPUT, 6)
val vec_nfregs = UFix(INPUT, 6)
}
class rocketDpathPCR extends Component
{
2011-11-09 23:52:17 +01:00
val io = new ioDpathPCR();
2012-01-02 01:09:40 +01:00
val reg_epc = Reg() { UFix() };
val reg_badvaddr = Reg() { UFix() };
val reg_ebase = Reg() { UFix() };
val reg_count = Reg() { UFix() };
val reg_compare = Reg() { UFix() };
val reg_cause = Reg() { Bits() };
2012-01-04 00:09:08 +01:00
val reg_tohost = Reg(resetVal = Bits(0, 64));
val reg_fromhost = Reg(resetVal = Bits(0, 64));
2012-05-09 12:09:22 +02:00
val reg_coreid = Reg() { Bits() }
2012-01-02 01:09:40 +01:00
val reg_k0 = Reg() { Bits() };
val reg_k1 = Reg() { Bits() };
val reg_ptbr = Reg() { UFix() };
2012-02-09 10:28:16 +01:00
val reg_vecbank = Reg(resetVal = Bits("b1111_1111", 8))
val reg_error_mode = Reg(resetVal = Bool(false));
2011-11-09 23:52:17 +01:00
val reg_status_vm = Reg(resetVal = Bool(false));
2012-03-24 21:03:31 +01:00
val reg_status_im = Reg(resetVal = Bits(0,SR_IM_WIDTH));
val reg_status_sx = Reg(resetVal = Bool(true));
val reg_status_ux = Reg(resetVal = Bool(true));
val reg_status_ec = Reg(resetVal = Bool(false));
val reg_status_ef = Reg(resetVal = Bool(false));
val reg_status_ev = Reg(resetVal = Bool(false));
val reg_status_s = Reg(resetVal = Bool(true));
val reg_status_ps = Reg(resetVal = Bool(false));
val reg_status_et = Reg(resetVal = Bool(false));
2011-11-14 12:24:02 +01:00
val r_irq_timer = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(true))
2011-11-13 09:27:57 +01:00
2012-05-24 19:33:15 +02:00
val rdata = Bits();
2012-07-26 12:28:07 +02:00
val raddr = Mux(io.r.en, io.r.addr, io.host.pcr_req.bits.addr(4,0))
io.host.pcr_rep.valid := io.host.pcr_req.fire()
2012-03-25 00:23:29 +01:00
io.host.pcr_rep.bits := rdata
val wen = io.w.en || !io.r.en && io.host.pcr_req.valid && io.host.pcr_req.bits.rw
2012-03-25 00:23:29 +01:00
val waddr = Mux(io.w.en, io.w.addr, io.host.pcr_req.bits.addr)
val wdata = Mux(io.w.en, io.w.data, io.host.pcr_req.bits.data)
io.host.pcr_req.ready := !io.w.en && !io.r.en
io.ptbr_wen := reg_status_vm.toBool && wen && (waddr === PCR_PTBR);
2012-03-24 21:03:31 +01:00
io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
io.evec := Mux(io.exception, reg_ebase, reg_epc)
2011-11-09 23:52:17 +01:00
io.ptbr := reg_ptbr;
io.host.debug.error_mode := reg_error_mode;
io.r.data := rdata;
2012-02-09 10:28:16 +01:00
io.vecbank := reg_vecbank
2012-02-09 11:35:09 +01:00
var cnt = UFix(0,4)
2012-02-09 10:28:16 +01:00
for (i <- 0 until 8)
cnt = cnt + reg_vecbank(i)
io.vecbankcnt := cnt(3,0)
val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
when (io.badvaddr_wen) {
2012-02-12 02:20:33 +01:00
reg_badvaddr := Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
}
2012-03-14 22:15:28 +01:00
when (io.vec_irq_aux_wen) {
reg_badvaddr := io.vec_irq_aux.toUFix
2012-03-14 22:15:28 +01:00
}
2012-02-12 02:20:33 +01:00
when (io.exception) {
when (!reg_status_et) {
reg_error_mode := Bool(true)
}
.otherwise {
reg_status_s := Bool(true);
reg_status_ps := reg_status_s;
reg_status_et := Bool(false);
reg_epc := io.pc;
reg_cause := io.cause;
}
}
2011-11-14 22:48:49 +01:00
2012-02-12 02:20:33 +01:00
when (io.eret) {
reg_status_s := reg_status_ps;
reg_status_et := Bool(true);
}
2012-02-12 02:20:33 +01:00
2011-11-13 09:27:57 +01:00
when (reg_count === reg_compare) {
2012-02-12 02:20:33 +01:00
r_irq_timer := Bool(true);
2011-11-13 09:27:57 +01:00
}
2012-02-12 02:20:33 +01:00
reg_count := reg_count + UFix(1);
2011-11-14 12:24:02 +01:00
io.irq_timer := r_irq_timer;
io.irq_ipi := r_irq_ipi;
io.host.ipi_req.valid := io.w.en && io.w.addr === PCR_SEND_IPI
io.host.ipi_req.bits := io.w.data
io.replay := io.host.ipi_req.valid && !io.host.ipi_req.ready
when (io.host.pcr_req.fire() && !io.host.pcr_req.bits.rw && io.host.pcr_req.bits.addr === PCR_TOHOST) { reg_tohost := UFix(0) }
2011-11-13 09:27:57 +01:00
when (wen) {
when (waddr === PCR_STATUS) {
reg_status_vm := wdata(SR_VM).toBool;
2012-03-24 21:03:31 +01:00
reg_status_im := wdata(SR_IM_WIDTH+SR_IM,SR_IM);
reg_status_sx := wdata(SR_S64).toBool;
reg_status_ux := wdata(SR_U64).toBool;
reg_status_s := wdata(SR_S).toBool;
reg_status_ps := wdata(SR_PS).toBool;
reg_status_ev := Bool(HAVE_VEC) && wdata(SR_EV).toBool;
reg_status_ef := Bool(HAVE_FPU) && wdata(SR_EF).toBool;
reg_status_ec := Bool(HAVE_RVC) && wdata(SR_EC).toBool;
reg_status_et := wdata(SR_ET).toBool;
2012-02-12 02:20:33 +01:00
}
2012-03-24 21:03:31 +01:00
when (waddr === PCR_EPC) { reg_epc := wdata(VADDR_BITS,0).toUFix; }
when (waddr === PCR_EVEC) { reg_ebase := wdata(VADDR_BITS-1,0).toUFix; }
when (waddr === PCR_COUNT) { reg_count := wdata(31,0).toUFix; }
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
2012-05-09 12:09:22 +02:00
when (waddr === PCR_COREID) { reg_coreid := wdata(15,0) }
when (waddr === PCR_FROMHOST) { when (reg_fromhost === UFix(0) || io.w.en) { reg_fromhost := wdata } }
when (waddr === PCR_TOHOST) { when (reg_tohost === UFix(0)) { reg_tohost := wdata } }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
2012-03-24 21:03:31 +01:00
when (waddr === PCR_K0) { reg_k0 := wdata; }
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
when (waddr === PCR_VECBANK) { reg_vecbank:= wdata(7,0) }
2012-02-12 02:20:33 +01:00
}
io.host.ipi_rep.ready := Bool(true)
when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
2012-03-25 00:23:29 +01:00
rdata := io.status // raddr === PCR_STATUS
switch (raddr) {
is (PCR_EPC) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
is (PCR_BADVADDR) { rdata := Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
is (PCR_EVEC) { rdata := Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
is (PCR_COUNT) { rdata := Cat(Fill(32, reg_count(31)), reg_count); }
is (PCR_COMPARE) { rdata := Cat(Fill(32, reg_compare(31)), reg_compare); }
is (PCR_CAUSE) { rdata := Cat(reg_cause(5), Bits(0,58), reg_cause(4,0)); }
2012-05-09 12:09:22 +02:00
is (PCR_COREID) { rdata := reg_coreid }
2012-03-25 00:23:29 +01:00
is (PCR_IMPL) { rdata := Bits(2) }
is (PCR_FROMHOST) { rdata := reg_fromhost; }
is (PCR_TOHOST) { rdata := reg_tohost; }
is (PCR_K0) { rdata := reg_k0; }
is (PCR_K1) { rdata := reg_k1; }
is (PCR_PTBR) { rdata := Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
is (PCR_VECBANK) { rdata := Cat(Bits(0, 56), reg_vecbank) }
is (PCR_VECCFG) { rdata := Cat(Bits(0, 40), io.vec_nfregs, io.vec_nxregs, io.vec_appvl) }
}
}
class ioReadPort extends Bundle()
{
2012-07-13 03:12:49 +02:00
val addr = UFix(INPUT, 5);
val en = Bool(INPUT);
2012-07-13 03:12:49 +02:00
val data = Bits(OUTPUT, 64);
}
class ioWritePort extends Bundle()
{
2012-07-13 03:12:49 +02:00
val addr = UFix(INPUT, 5);
val en = Bool(INPUT);
2012-07-13 03:12:49 +02:00
val data = Bits(INPUT, 64);
}
class ioRegfile extends Bundle()
{
val r0 = new ioReadPort();
val r1 = new ioReadPort();
val w0 = new ioWritePort();
}
class rocketDpathRegfile extends Component
{
override val io = new ioRegfile();
2012-01-14 05:04:11 +01:00
val regfile = Mem(32){ Bits(width=64) }
2012-06-06 11:47:22 +02:00
when (io.w0.en) { regfile(io.w0.addr) := io.w0.data }
io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
}