Klemens Schölhorn klemens
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klemens pushed to ml507 at riscv/fpga-shells 2018-04-30 00:42:21 +02:00
9c06418352 Add terminal/dvi io (unsing the same clock for now)
b2b19cc822 Add clock and proper reset feedback to ml507
5db71d11c2 Fix polarity of buttons and dips on the ml507
f4ae1d469f Remove unused signals (pcie, mem) from ml507 shell
0b421d5645 Remove incorrect jtag pin constraints form ml507
Compare 6 commits »
klemens pushed to boot-test at riscv/freedom 2018-04-24 00:53:08 +02:00
738356e79d TEST: Remove memory access from bootloader and some GPIO fun
1cb558d2ea ml507: Don't accept any messages in the stub memory slave
d749f87696 ml507: Remove redundant clock definition
c04243cf03 TEST: Simple boot tests without memory interaction
Compare 4 commits »
klemens pushed to ml507 at riscv/freedom 2018-04-24 00:52:40 +02:00
1cb558d2ea ml507: Don't accept any messages in the stub memory slave
d749f87696 ml507: Remove redundant clock definition
Compare 2 commits »
klemens pushed to ml507 at riscv/freedom 2018-04-19 01:36:23 +02:00
c10d2378e7 Disable TLMonitors
2b5509009c Increase gpio width to 8
06a623a05a Update to latest ml507 shell
54e61b527c Disable JTAG support for now
Compare 4 commits »
klemens pushed to boot-test at riscv/freedom 2018-04-19 01:36:11 +02:00
c04243cf03 TEST: Simple boot tests without memory interaction
c10d2378e7 Disable TLMonitors
2b5509009c Increase gpio width to 8
06a623a05a Update to latest ml507 shell
59a3241ff5 TEST: Simple boot tests without memory interaction
Compare 6 commits »
klemens pushed to boot-test at riscv/freedom 2018-04-18 00:55:14 +02:00
59a3241ff5 TEST: Simple boot tests without memory interaction
klemens pushed to ml507 at riscv/fpga-shells 2018-04-18 00:53:28 +02:00
2ff28e6af6 Add status indication led for the reset button
41362a1cb5 Remove unused UART signals (rs and cs) from ml507
Compare 2 commits »
klemens pushed to ml507 at riscv/freedom 2018-04-18 00:53:11 +02:00
54e61b527c Disable JTAG support for now
48f3a7e590 Reduce rocket to a single core
7449f52b9a Update to latest ml507 shell
Compare 3 commits »
klemens pushed to ml507 at riscv/freedom 2018-04-12 00:51:13 +02:00
212821fe4d Switch to the new ML507Shell
9afecc1695 Switch to the new ML507Shell
Compare 2 commits »
klemens deleted branch virtex5 from riscv/freedom 2018-04-12 00:49:44 +02:00
klemens pushed to ml507 at riscv/freedom 2018-04-12 00:49:27 +02:00
9afecc1695 Switch to the new ML507Shell
8e4eaf6603 Add TLMemoryML507 stub and integration
0134a8f4dc Remove vc707 memory interface from ml507
klemens pushed to master at riscv/fpga-shells 2018-04-12 00:46:45 +02:00
9d02f530fc vc707shell: work-around too many '++'s => stack overflow issue
080119ec7a chiplink: add pinout (#20)
0ca9f2bb66 periphery: bus api update (#17)
1dda525578 prologue: support the absence of an xdc/tcl constraint file
6df6db25de Merge pull request #18 from sifive/dynamic-clock-groups
Compare 16 commits »
klemens pushed to master at riscv/fpga-shells 2018-04-12 00:46:40 +02:00
klemens pushed to ml507 at riscv/fpga-shells 2018-04-12 00:45:56 +02:00
e9625bf8ee Add initial ML507Shell stub based on VC707Shell
9d02f530fc vc707shell: work-around too many '++'s => stack overflow issue
080119ec7a chiplink: add pinout (#20)
0ca9f2bb66 periphery: bus api update (#17)
1dda525578 prologue: support the absence of an xdc/tcl constraint file
klemens pushed to master at riscv/freedom 2018-04-11 20:10:59 +02:00
cd9a525a66 Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87 U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56 Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627 Correct GPIO/SPI/UART base addresse for vc707 sdboot
fff18810cd Merge pull request #48 from sifive/chiplink
Compare 8 commits »
klemens pushed to refs/remotes/origin/master at riscv/freedom 2018-04-11 20:10:35 +02:00
cd9a525a66 Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87 U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56 Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627 Correct GPIO/SPI/UART base addresse for vc707 sdboot
fff18810cd Merge pull request #48 from sifive/chiplink
klemens pushed to virtex5 at riscv/freedom 2018-04-11 20:10:10 +02:00
5fdadd244c Add makefile and config for the ml507 board
cd9a525a66 Merge pull request #50 from sifive/update_readme_vc707_vivado2016dot4
0e77cb9d87 U500 VC707 FPGA Dev Kit : update required Vivado version from 2016.1 to 2016.4 to fix synthesis bug effecting debug module
c0a2869e56 Merge pull request #49 from sifive/update_vc707_sdboot
0663bb7627 Correct GPIO/SPI/UART base addresse for vc707 sdboot
Compare 11 commits »
klemens pushed to master at band/website 2018-03-23 17:01:00 +01:00
b121c8fa7d Add link to the new forum!
klemens pushed to virtex5 at riscv/freedom 2018-03-21 01:43:24 +01:00
8f56113696 Fix scala version
klemens pushed to master at riscv/freedom 2018-03-21 01:40:07 +01:00
9b3763ea92 Merge pull request #47 from sifive/bump-repos
1445a381a1 platforms: fixup to new package names
6c9b159659 submodules: bump again for the latest refactor
c076d53fe9 fpga-shells: bump to fix timing closure
756e2e82a1 build: update all submodules to their current master