Add makefile and config for the ml507 board

The config is based on the u500vc707devkit config.
This commit is contained in:
Klemens Schölhorn 2018-03-21 01:31:56 +01:00
parent cd9a525a66
commit 5fdadd244c
4 changed files with 195 additions and 0 deletions

24
Makefile.u500ml507devkit Normal file
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# See LICENSE for license details.
base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
BUILD_DIR := $(base_dir)/builds/u500ml507devkit
FPGA_DIR := $(base_dir)/fpga-shells/xilinx
MODEL := U500ML507DevKitFPGAChip
PROJECT := sifive.freedom.unleashed.u500ml507devkit
export CONFIG_PROJECT := sifive.freedom.unleashed.u500ml507devkit
export CONFIG := U500ML507DevKitConfig
export BOARD := ml507
export BOOTROM_DIR := $(base_dir)/bootrom/sdboot
rocketchip_dir := $(base_dir)/rocket-chip
sifiveblocks_dir := $(base_dir)/sifive-blocks
VSRCS := \
$(rocketchip_dir)/vsrc/AsyncResetReg.v \
$(rocketchip_dir)/vsrc/plusarg_reader.v \
$(sifiveblocks_dir)/vsrc/SRLatch.v \
$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
$(FPGA_DIR)/$(BOARD)/vsrc/sdio.v \
$(FPGA_DIR)/$(BOARD)/vsrc/ml507reset.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
include common.mk

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// See LICENSE for license details.
package sifive.freedom.unleashed.u500ml507devkit
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system._
import freechips.rocketchip.tile._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.fpgashells.devices.xilinx.xilinxvc707mig.{MemoryXilinxDDRKey,XilinxVC707MIGParams}
// Default FreedomUML507Config
class FreedomUML507Config extends Config(
new WithJtagDTM ++
new WithNMemoryChannels(1) ++
new WithNBigCores(4) ++
new BaseConfig
)
// Freedom U500 ML507 Dev Kit Peripherals
class U500ML507DevKitPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(
UARTParams(address = BigInt(0x64000000L)))
case PeripherySPIKey => List(
SPIParams(rAddress = BigInt(0x64001000L)))
case PeripheryGPIOKey => List(
GPIOParams(address = BigInt(0x64002000L), width = 4))
case PeripheryMaskROMKey => List(
MaskROMParams(address = 0x10000, name = "BootROM"))
})
// Freedom U500 ML507 Dev Kit
class U500ML507DevKitConfig extends Config(
new WithNExtTopInterrupts(0) ++
new U500ML507DevKitPeripherals ++
new FreedomUML507Config().alter((site,here,up) => {
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=128)
case PeripheryBusKey => up(PeripheryBusKey, site).copy(frequency = 50000000) // 50 MHz hperiphery
case MemoryXilinxDDRKey => XilinxVC707MIGParams(address = Seq(AddressSet(0x80000000L,0x40000000L-1))) //1GB
case DTSTimebase => BigInt(1000000)
case ExtMem => up(ExtMem).copy(size = 0x40000000L)
case JtagDTMKey => new JtagDTMConfig (
idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
idcodePartNum = 0x000, // Decided to simplify.
idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
debugIdleCycles = 5) // Reasonable guess for synchronization
})
)

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// See LICENSE for license details.
package sifive.freedom.unleashed.u500ml507devkit
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.shell.xilinx.vc707shell._
import sifive.fpgashells.ip.xilinx.{IOBUF}
//-------------------------------------------------------------------------
// PinGen
//-------------------------------------------------------------------------
object PinGen {
def apply(): BasePin = {
new BasePin()
}
}
//-------------------------------------------------------------------------
// U500ML507DevKitFPGAChip
//-------------------------------------------------------------------------
class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
extends VC707Shell
with HasDDR3
with HasDebugJTAG {
//-----------------------------------------------------------------------
// DUT
//-----------------------------------------------------------------------
// Connect the clock to the 50 Mhz output from the PLL
dut_clock := clk50
withClockAndReset(dut_clock, dut_reset) {
val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
//---------------------------------------------------------------------
// Connect peripherals
//---------------------------------------------------------------------
connectDebugJTAG(dut)
connectSPI (dut)
connectUART (dut)
connectMIG (dut)
//---------------------------------------------------------------------
// GPIO
//---------------------------------------------------------------------
val gpioParams = p(PeripheryGPIOKey)
val gpio_pins = Wire(new GPIOPins(() => PinGen(), gpioParams(0)))
GPIOPinsFromPort(gpio_pins, dut.gpio(0))
gpio_pins.pins.foreach { _.i.ival := Bool(false) }
gpio_pins.pins.zipWithIndex.foreach {
case(pin, idx) => led(idx) := pin.o.oval
}
// tie to zero
for( idx <- 7 to 4 ) { led(idx) := false.B }
}
}

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// See LICENSE for license details.
package sifive.freedom.unleashed.u500ml507devkit
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.system._
import sifive.blocks.devices.gpio._
import sifive.blocks.devices.spi._
import sifive.blocks.devices.uart._
import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
//-------------------------------------------------------------------------
// U500ML507DevKitSystem
//-------------------------------------------------------------------------
class U500ML507DevKitSystem(implicit p: Parameters) extends RocketSubsystem
with HasPeripheryMaskROMSlave
with HasPeripheryDebug
with HasSystemErrorSlave
with HasPeripheryUART
with HasPeripherySPI
with HasPeripheryGPIO
with HasMemoryXilinxVC707MIG {
override lazy val module = new U500ML507DevKitSystemModule(this)
}
class U500ML507DevKitSystemModule[+L <: U500ML507DevKitSystem](_outer: L)
extends RocketSubsystemModuleImp(_outer)
with HasRTCModuleImp
with HasPeripheryDebugModuleImp
with HasPeripheryUARTModuleImp
with HasPeripherySPIModuleImp
with HasPeripheryGPIOModuleImp
with HasMemoryXilinxVC707MIGModuleImp {
// Reset vector is set to the location of the mask rom
val maskROMParams = p(PeripheryMaskROMKey)
global_reset_vector := maskROMParams(0).address.U
}