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1cb558d2ea
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d749f87696 |
@ -34,8 +34,6 @@ class U500ML507DevKitFPGAChip(implicit override val p: Parameters)
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// DUT
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//-----------------------------------------------------------------------
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// Connect the clock to the 50 Mhz output from the PLL
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dut_clock := clk50
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withClockAndReset(dut_clock, dut_reset) {
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val dut = Module(LazyModule(new U500ML507DevKitSystem).module)
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@ -46,10 +46,10 @@ class TLMemoryML507(c: MemoryML507Params)(implicit p: Parameters) extends LazyMo
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val (in, edge)= node.in(0)
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// Tie off unused channels
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in.a.ready := Bool(true)
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in.a.ready := Bool(false)
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.c.ready := Bool(false)
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in.d.valid := Bool(false)
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in.e.ready := Bool(true)
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in.e.ready := Bool(false)
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}
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}
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