Klemens Schölhorn klemens
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klemens pushed to ml507 at riscv/freedom 2018-05-10 03:18:26 +02:00
291a765b8d Switch to new XilinxML507MIG and connect top level signals
7b46ed6b7c Move ml507 mig TL stub into fpga-shells
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klemens pushed to ml507 at riscv/fpga-shells 2018-05-10 03:18:17 +02:00
7e53be49f9 Fix memory controller signal name
77694a6741 Add clock generation for the mig
589e9960c0 Move XilinxML507MIGToTL and MIG into a separate clock domain
2707fa59a4 Add XilinxML507MIG periphery and connect top level signals
3797385a8c Import ml507 mig TL implementation stub
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klemens pushed to master at band/website 2018-05-05 19:48:55 +02:00
9bd81a8dc2 Revert ":P" (use sane colors again)
klemens pushed to master at band/kicad-libs 2018-05-03 19:37:23 +02:00
0511dd8279 Add symbol and footprint for microSD cards
02da34a012 Add schematic for a constant voltage source
2fa18a289e Add schematic symbol for a oscilloscope
3a99be9849 Add schematic symbol for a function generator
klemens pushed to boot-test at riscv/freedom 2018-05-03 01:58:44 +02:00
7d322bc70e BOOT-TEST: No memory access, terminal writes, GPIO square wave
0cb89fd675 Add fragmenter in front of TLMemoryML507 and implementation notes
e087f544a6 BOOT-TEST: No memory access, terminal writes, GPIO square wave
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klemens pushed to ml507 at riscv/freedom 2018-05-03 01:58:40 +02:00
0cb89fd675 Add fragmenter in front of TLMemoryML507 and implementation notes
klemens pushed to boot-test at riscv/freedom 2018-05-01 00:16:01 +02:00
e087f544a6 BOOT-TEST: No memory access, terminal writes, GPIO square wave
7a514c6477 Point all submodules to tiband
26db334db1 BOOT-TEST: No memory access, terminal writes, GPIO square wave
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klemens pushed to ml507 at riscv/fpga-shells 2018-05-01 00:15:36 +02:00
79b53cf2ae Add dip switches and clean up top interface
klemens pushed to ml507 at riscv/freedom 2018-05-01 00:15:19 +02:00
7a514c6477 Point all submodules to tiband
klemens pushed to ml507 at riscv/rocket-chip 2018-05-01 00:13:32 +02:00
6df42fc360 ml507: readmemh does not support dynamic paths on ISE
4ba8acb4aa TLRAM: add support for ECC (#1304)
12583af4a8 buswrapper: remove buffer chains from api (#1303)
4cfae27efd Implement Hauser misa.C misalignment proposal (#1301)
7f96da2288 ECC: support poison during encode (#1166)
klemens pushed to boot-test at riscv/freedom 2018-05-01 00:12:17 +02:00
26db334db1 BOOT-TEST: No memory access, terminal writes, GPIO square wave
e57dfd0f63 Update rocket-chip to fix rom generation
df44d1a3bc Make DIP switches available as GPIO register
844ab0be8c BOOT-TEST: No memory access, terminal writes, GPIO square wave
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klemens pushed to ml507 at riscv/freedom 2018-05-01 00:12:11 +02:00
e57dfd0f63 Update rocket-chip to fix rom generation
df44d1a3bc Make DIP switches available as GPIO register
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klemens pushed to ml507 at riscv/sifive-blocks 2018-04-30 22:56:17 +02:00
48d8524c4a Move terminal into own clock domain using AsyncQueue
klemens pushed to ml507 at riscv/fpga-shells 2018-04-30 22:56:13 +02:00
5bcc4e82fd Generate separate processor and terminal clocks
klemens pushed to boot-test at riscv/freedom 2018-04-30 22:56:02 +02:00
844ab0be8c BOOT-TEST: No memory access, terminal writes, GPIO square wave
4f950772a1 Use 80 MHz for rocket and 48 MHz for the terminal
b30e713242 BOOT-TEST: No memory access, terminal writes, GPIO square wave
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klemens pushed to ml507 at riscv/freedom 2018-04-30 22:55:12 +02:00
4f950772a1 Use 80 MHz for rocket and 48 MHz for the terminal
klemens pushed to master at band/website 2018-04-30 21:17:38 +02:00
73f4547e62 Add favicon
f6b0575f6a Use logo with text as brand item in the header
c1dea6ee1b Add tux as background instead of fixed image
ad7970df5d Use forum background color and remove vignette
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klemens pushed to boot-test at riscv/freedom 2018-04-30 00:55:14 +02:00
b30e713242 BOOT-TEST: No memory access, terminal writes, GPIO square wave
97eeb7af29 Add terminal peripheral (in same clock domain for now)
738356e79d TEST: Remove memory access from bootloader and some GPIO fun
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klemens pushed to ml507 at riscv/freedom 2018-04-30 00:54:45 +02:00
97eeb7af29 Add terminal peripheral (in same clock domain for now)
klemens pushed to ml507 at riscv/sifive-blocks 2018-04-30 00:48:34 +02:00
d7b9834d96 Add TLTerminal (write-only terminal TL slave)
7ac56c01af Merge pull request #53 from sifive/chiplink
ac55313e8e msi: add a MSIMaster to bridge interrupts over ChipLink
3db375ef43 devices: add support for the chiplink protocol
48a9acc8a4 Merge pull request #52 from sifive/spi_sync