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@ -13,6 +13,7 @@ import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.chiplink._
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import sifive.blocks.devices.terminal._
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import sifive.fpgashells.ip.xilinx.{IBUFDS, PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_sys_clock , vc707reset}
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@ -30,47 +31,6 @@ trait HasDebugJTAG { this: ML507Shell =>
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val jtag_TDO = IO(Output(Bool()))
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def connectDebugJTAG(dut: HasPeripheryDebugModuleImp, fmcxm105: Boolean = true): SystemJTAGIO = {
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ElaborationArtefacts.add(
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"""debugjtag.vivado.tcl""",
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"""set vc707debugjtag_vivado_tcl_dir [file dirname [file normalize [info script]]]
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add_files -fileset [current_fileset -constrset] [glob -directory $vc707debugjtag_vivado_tcl_dir {*.vc707debugjtag.xdc}]"""
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)
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if(fmcxm105) {
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//VC707 constraints for Xilinx FMC XM105 Debug Card
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ElaborationArtefacts.add(
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"""vc707debugjtag.xdc""",
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"""set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN R32 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN W36 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN W37 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN V40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
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)
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} else {
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//VC707 constraints for Olimex connect to LCD panel header
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ElaborationArtefacts.add(
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"""vc707debugjtag.xdc""",
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"""
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#Olimex Pin Olimex Function LCD Pin LCD Function FPGA Pin
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#1 VREF 14 5V
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#3 TTRST_N 1 LCD_DB7 AN40
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#5 TTDI 2 LCD_DB6 AR39
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#7 TTMS 3 LCD_DB5 AR38
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#9 TTCK 4 LCD_DB4 AT42
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#11 TRTCK NC NC NC
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#13 TTDO 9 LCD_E AT40
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#15 TSRST_N 10 LCD_RW AR42
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#2 VREF 14 5V
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#18 GND 13 GND
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_TCK_IBUF]
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set_property -dict { PACKAGE_PIN AT42 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TCK}]
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set_property -dict { PACKAGE_PIN AR38 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TMS}]
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set_property -dict { PACKAGE_PIN AR39 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDI}]
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set_property -dict { PACKAGE_PIN AT40 IOSTANDARD LVCMOS18 PULLUP TRUE } [get_ports {jtag_TDO}] """
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)
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}
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val djtag = dut.debug.systemjtag.get
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djtag.jtag.TCK := jtag_TCK
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@ -98,7 +58,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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// active high reset
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val reset = IO(Input(Bool()))
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val reset_led = IO(Output(Bool()))
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// LED
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val led = IO(Vec(8, Output(Bool())))
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@ -113,21 +72,26 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val sdio_dat = IO(Analog(4.W))
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//Buttons
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val btn_0 = IO(Analog(1.W))
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val btn_1 = IO(Analog(1.W))
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val btn_2 = IO(Analog(1.W))
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val btn_3 = IO(Analog(1.W))
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val btn_0 = IO(Input(Bool()))
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val btn_1 = IO(Input(Bool()))
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val btn_2 = IO(Input(Bool()))
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val btn_3 = IO(Input(Bool()))
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//Sliding switches
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val sw_0 = IO(Analog(1.W))
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val sw_1 = IO(Analog(1.W))
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val sw_2 = IO(Analog(1.W))
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val sw_3 = IO(Analog(1.W))
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val sw_4 = IO(Analog(1.W))
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val sw_5 = IO(Analog(1.W))
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val sw_6 = IO(Analog(1.W))
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val sw_7 = IO(Analog(1.W))
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val sw_0 = IO(Input(Bool()))
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val sw_1 = IO(Input(Bool()))
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val sw_2 = IO(Input(Bool()))
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val sw_3 = IO(Input(Bool()))
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val sw_4 = IO(Input(Bool()))
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val sw_5 = IO(Input(Bool()))
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val sw_6 = IO(Input(Bool()))
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val sw_7 = IO(Input(Bool()))
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// Feedback
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val clock_led = IO(Output(Clock()))
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val reset_led = IO(Output(Bool()))
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val dvi = IO(new TerminalDVIIO)
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//-----------------------------------------------------------------------
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// Wire declrations
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@ -138,7 +102,6 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val dut_clock = Wire(Clock())
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val dut_reset = Wire(Bool())
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val dut_resetn = Wire(Bool())
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val dut_ndreset = Wire(Bool())
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@ -149,20 +112,7 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val do_reset = Wire(Bool())
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val mig_mmcm_locked = Wire(Bool())
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val mig_sys_reset = Wire(Bool())
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val mig_clock = Wire(Clock())
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val mig_reset = Wire(Bool())
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val mig_resetn = Wire(Bool())
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val pcie_dat_reset = Wire(Bool())
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val pcie_dat_resetn = Wire(Bool())
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val pcie_cfg_reset = Wire(Bool())
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val pcie_cfg_resetn = Wire(Bool())
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val pcie_dat_clock = Wire(Clock())
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val pcie_cfg_clock = Wire(Clock())
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val mmcm_lock_pcie = Wire(Bool())
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val clk_locked = Wire(Bool())
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//-----------------------------------------------------------------------
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@ -175,17 +125,15 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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// Allow the debug module to reset everything. Resets the MIG
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sys_reset := reset | dut_ndreset
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// Status LED for reset
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reset_led := reset
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//-----------------------------------------------------------------------
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// Clock Generator
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//-----------------------------------------------------------------------
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//50MHz (37.5MHz)
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// 48 MHz (TMP, normally 50 MHz)
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val ml507_sys_clock = Module(new ml507_sys_clock)
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ml507_sys_clock.io.CLKIN_IN := sys_clock.asUInt
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val clk50 = ml507_sys_clock.io.CLKFX_OUT
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clk_locked := ml507_sys_clock.io.LOCKED_OUT
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// DUT clock
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dut_clock := clk50
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@ -194,34 +142,31 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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// System reset
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//-----------------------------------------------------------------------
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do_reset := !mig_mmcm_locked || !mmcm_lock_pcie || mig_sys_reset
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mig_resetn := !mig_reset
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dut_resetn := !dut_reset
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pcie_dat_resetn := !pcie_dat_reset
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pcie_cfg_resetn := !pcie_cfg_reset
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do_reset := !clk_locked || sys_reset
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// TODO: adapt for ml507?
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val safe_reset = Module(new vc707reset)
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safe_reset.io.areset := do_reset
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safe_reset.io.clock1 := mig_clock
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mig_reset := safe_reset.io.reset1
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safe_reset.io.clock2 := pcie_dat_clock
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pcie_dat_reset := safe_reset.io.reset2
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safe_reset.io.clock3 := pcie_cfg_clock
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pcie_cfg_reset := safe_reset.io.reset3
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safe_reset.io.clock1 := dut_clock
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safe_reset.io.clock2 := dut_clock
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safe_reset.io.clock3 := dut_clock
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safe_reset.io.clock4 := dut_clock
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dut_reset := safe_reset.io.reset4
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//overrided in connectMIG and connect PCIe
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//provide defaults to allow above reset sequencing logic to work without both
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mig_clock := dut_clock
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pcie_dat_clock := dut_clock
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pcie_cfg_clock := dut_clock
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mig_mmcm_locked := UInt("b1")
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mmcm_lock_pcie := UInt("b1")
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// Setup feedback
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clock_led := dut_clock
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reset_led := dut_reset
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//-----------------------------------------------------------------------
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// Terminal
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//-----------------------------------------------------------------------
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def connectTerminal(dut: HasPeripheryTerminalModuleImp): Unit = {
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dvi <> dut.dvi
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dut.terminal.clk := dut_clock
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dut.terminal.reset := dut_reset
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}
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//-----------------------------------------------------------------------
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// UART
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