06f0d20742
Add missing cloneType methods to pin bundles
2017-07-20 11:36:31 -07:00
00086c26e6
i2c: Remove pluralization on the bundle name, i2c not i2cs
2017-07-20 10:53:44 -07:00
ef4f2ed888
Remove pluralization on interface names. Require clocks and resets explicitly when necessary
2017-07-19 14:51:50 -07:00
4d74e8f67f
Make it possible to adjust the type of pad controls used,
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and seperate out some of the "GPIO Peripheral" from "Pin Control"
2017-07-19 08:01:42 -07:00
fb9dd31374
Refactor package hierarchy. ( #25 )
2017-07-07 10:48:57 -07:00
66b2fd11bd
vc707 axi enhancements ( #24 )
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1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
2017-06-30 12:36:33 -07:00
886680af49
mig: fix MemoryDevice to use 'reg' properly
2017-06-29 13:41:30 -07:00
a8e20f447c
spi: include mem region ( #23 )
2017-06-28 17:46:45 -07:00
3d8c502fce
diplomacy: add reg-names to devices ( #22 )
2017-06-28 17:45:18 -07:00
2154e9eb3f
gpio: Make IOF optional ( #21 )
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* gpio: Make IOF optional
* IOF: Make the default false
2017-06-19 12:41:38 -07:00
473464eaa9
make some base bundle classes easier to clone ( #20 )
2017-06-14 19:47:56 -07:00
90d3931f5a
spi: add dts ranges field for memory mapped spi ( #19 )
2017-06-14 17:06:55 -07:00
8bfda68858
More Peripheral-to-pins cleanups
2017-06-13 11:00:29 -07:00
b3f656affe
UART: actually return the pins, not just the module. We should do this for the other peripherals as well
2017-06-12 18:08:35 -07:00
b06b80dccd
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:51 -07:00
7c118790cb
GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.
2017-06-12 17:53:08 -07:00
d4bb8a77ea
periphery: convert periphery bundle traits to work with system-level multi-io module
2017-06-12 16:57:47 -07:00
79f64de12c
peripheral_options: Actually compiles
2017-06-09 13:53:22 -07:00
29226701a8
SPIFlash: make it listable
2017-06-08 16:29:01 -07:00
c89f163c0d
GPIO: Make GPIO peripheral another listable one
2017-06-08 16:25:20 -07:00
0ca609d324
vc707axi: track rocketchip API changes ( #16 )
2017-06-02 15:56:18 -07:00
0f8722f80c
uart: power-on with the right divider for the design ( #15 )
2017-05-13 23:38:20 -07:00
c4c158963c
vc707mig: use an external ibuf
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This makes it possible to also drive a PLL of our own from the crystal.
2017-05-12 23:07:10 -07:00
0ed21ba465
xilinxvc707pciex1: push to a dedicated clock domain
2017-05-12 23:02:44 -07:00
b3f9607512
xilinx mig: put a buffer infront of the controller ( #13 )
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This makes placement of the L2 and DDR controller easier.
2017-05-11 11:50:07 -07:00
178ac84b59
xilinxvc707pciex1: better wrapper for AXI4-Lite control node ( #12 )
2017-05-08 01:08:37 -07:00
9cb80ac913
Merge pull request #10 from sifive/axi-mmio
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axi4: switch to new pipelined converters
2017-05-03 11:46:30 -07:00
75d6a7c6ea
spi: Fix off-by-one error in calculating cycles per data frame
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Issue: Configuring the frame length to certain values causes incorrect
operation.
Symptoms: Certain frame lengths result in the master sending one extra
clock pulse. The slave device may then become desynchronized.
Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
* Serial mode: 0, 2, 4, 6, 8
* Dual mode: 0, 1, 3, 5, 7, 8
* Quad mode: 0, 1, 2, 3, 5, 6, 7, 8
2017-05-02 12:35:34 -07:00
eea10f5129
spi: Fix io.port.dq(3) output enable
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Issue: The output enable signal for DQ[3] is not driven properly.
Symptoms: Output data from master to slave is not properly transmitted
in quad mode. Data received from the slave is unaffected.
Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol. Do not use the Native Quad SPI protocol.
2017-05-02 12:07:37 -07:00
a24fa9b444
axi4: switch to new pipelined converters
2017-04-26 13:10:50 -07:00
6eddf517a3
Merge pull request #9 from sifive/vc707_mig_analog_inout
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Use _chisel3 analog for MIG inout
2017-04-25 10:18:46 -07:00
b882d6da93
Use _chisel3 analog for MIG inout
2017-04-25 10:15:00 -07:00
b1dfcfc0b0
Added stall for read after write ( #8 )
2017-04-25 09:14:00 -07:00
9ba47b76c6
MockAON: Accept the non-debug interrupt as an input to overall reset.
2017-04-07 16:42:32 -07:00
70ac4044d1
spi: correct polarity of FIRRTL combo loop detection workaround.
2017-03-31 13:49:34 -07:00
1af6ce1c85
Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD
2017-03-30 20:01:30 -07:00
6a3b5e1a31
"Fix" false combinational loop through SPIArbiter
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Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
2017-03-30 19:12:15 -07:00
3c2277447d
rename l2FrontendBus as fsb
2017-03-25 19:51:53 -07:00
e2073feef8
rename l2FrontendBus as fsb
2017-03-24 21:38:31 -07:00
faeb14dc5a
JTAG: make TRSTn optional for all helpers as well to match the IO.
2017-03-24 17:27:55 -07:00
c1872c574b
update TLRegisterNode to take Seq of AddressSet
2017-03-21 22:12:37 -07:00
c6d7326669
TLSPI: address parameter must now be a sequence.
2017-03-21 17:51:33 -07:00
77246eaada
Adjust JTAG for rocket-chip changes
2017-03-14 14:52:39 -07:00
25356957fe
Merge remote-tracking branch 'origin/master' into debug-0.13
2017-03-10 14:09:24 -08:00
062203ae18
xilinx pcie: add the high PCIe address bits (physical path)
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The format is taken from here:
http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
2017-03-02 21:22:41 -08:00
46aa6b0ac4
devices: include DTS meta-data
2017-03-02 20:39:30 -08:00
baccd5ada2
devices: create periphery keys for all devices
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Standardize how they are connected to the periphery bus
2017-03-02 20:39:25 -08:00
bf9b81f2bc
jtag: The jtag interfaces have moved to a different package.
2017-03-02 14:46:34 -08:00
03be9aba67
Use HomogenousBag to handle lists of peripherals
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Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
2017-02-16 17:52:24 -08:00
a915e84a9e
Merge remote-tracking branch 'origin/master' into i2c
2017-02-09 18:45:35 -08:00
095cb158dd
Flipped polarity of output enables to match Guava pins logic
2017-02-09 11:37:40 -08:00
72e4b60d81
Made regs 32-bit word aligned to match the rest of the system
2017-02-09 11:36:19 -08:00
9ca71c0cf2
Added note: WISHBONE interface replaced by Tilelink2
2017-02-07 16:14:28 -08:00
c311b6ec63
Added license
2017-02-07 15:58:04 -08:00
5a0d084b38
Renamed i2cDevices to i2c
2017-02-06 10:39:47 -08:00
88e4c8ee20
xilinx mig: track changes in rocket-chip
2017-02-03 18:17:58 -08:00
d474b5ceb2
Addressing comments: bool style, comments, removed suggestName
2017-02-03 18:10:03 -08:00
3781d1fb1a
Bug fixes: passing OC WB test
2017-02-03 16:41:59 -08:00
c010a1557a
sifive-blocks: trust diplomacy to get names right
2017-02-01 13:53:54 -08:00
2cc1012fa2
Completed Chisel RTL (not tested yet)
2017-01-31 17:20:53 -08:00
535be3e976
spi: work around ucb-bar/chisel3#472
2017-01-31 14:03:14 -08:00
5b6760394d
xilinx ip: adjust to new diplomacy API
2017-01-30 11:33:30 -08:00
9d2a173b15
Initial (compilable) version of I2C (no actual logic yet)
2017-01-24 14:58:01 -08:00
d61d86e084
xilinx pcie: put buffers before the outputs to the controller
2017-01-20 22:38:27 -08:00
c68e44ec55
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
45c491cd69
LazyModule: provide Parameters
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This tracks PR #478 in rocketchip.
2016-12-07 13:21:20 -08:00
1443834186
xilinx pcie: bytes, not bits
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This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
2016-12-06 16:13:12 -08:00
ca7555bd4d
RegMapFIFO: amoor.w can do thread-safe TX
2016-12-02 17:48:17 -08:00
7916ef5249
Initial commit.
2016-11-29 04:08:44 -08:00
Megan Wachs
Henry Cook
Wesley W. Terpstra
Albert Ou
Henry Styles
solomatnikov
Jack Koenig
Yunsup Lee
Alex Solomatnikov
Alex Solomatnikov
SiFive