riscv/rocket-chip
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  • e723a3f42b MemoryBus: fanout the A for performance Wesley W. Terpstra 2017-09-07 16:01:42 -0700
  • 6879f5bfb1 tilelink: Xbar now allows for fanout control Wesley W. Terpstra 2017-09-07 15:42:40 -0700
  • e831acba9c adapters: support bulk connections Wesley W. Terpstra 2017-09-07 15:07:08 -0700
  • 06a244f9f9 diplomacy: rename {Left,Right}Star to refer to {Source,Sink}Cardinality Wesley W. Terpstra 2017-09-07 15:03:09 -0700
  • bef593c21a diplomacy: edges now capture their Parameters Wesley W. Terpstra 2017-09-07 14:56:09 -0700
  • 80ed27683e diplomacy: protect against API leakage Wesley W. Terpstra 2017-09-07 14:33:09 -0700
  • 1365c5f90c diplomacy: implement DisableMonitors scope Wesley W. Terpstra 2017-09-07 14:25:33 -0700
  • a450357744 tilelink: Monitor construction method is unconditional Wesley W. Terpstra 2017-09-07 13:41:26 -0700
  • 7a8364ef08 diplomacy: leverage new Parameters defaults Wesley W. Terpstra 2017-09-07 13:33:07 -0700
  • 655a08f12e config: support default values for Field[T] keys Wesley W. Terpstra 2017-09-07 13:29:59 -0700
  • 09d8d476c5 config: require Parameters keys to be Field[T] Wesley W. Terpstra 2017-09-07 13:29:14 -0700
  • 42f1ae27fc Xbar: use the IdentityModule to encourage wider fanout Wesley W. Terpstra 2017-09-06 16:07:58 -0700
  • 5626cdd18f util: add the IdentityModule, useful to dedup wires Wesley W. Terpstra 2017-09-06 16:07:31 -0700
  • 1a87ed1193 coreplex: add externalSlaveBuffers configuration option Wesley W. Terpstra 2017-09-06 14:58:34 -0700
  • fd8a51a910 coreplex: rename externalBuffers to externalMasterBuffers Wesley W. Terpstra 2017-09-06 14:40:13 -0700
  • 4911a7d44f tilelink Bus: toAsyncSlaves now supports BufferChains Wesley W. Terpstra 2017-09-06 14:42:47 -0700
  • 040f7e1d49 tilelink: add Bus.toSyncSlaves for easy BufferChain attachment Wesley W. Terpstra 2017-09-06 14:58:04 -0700
  • d5c6494f59 tilelink: Bus.toRationalSlaves can have a BufferChain Wesley W. Terpstra 2017-09-06 14:37:22 -0700
  • 80965e8230 tilelink Buffer: use new :=? adapter API Wesley W. Terpstra 2017-09-06 15:44:54 -0700
  • 1b705f62f6 diplomacy: support :=? for unknown star inference Wesley W. Terpstra 2017-09-06 15:30:25 -0700
  • 6bfea86dbf config: support p.lift(key) to optionally return a value Wesley W. Terpstra 2017-09-06 15:04:46 -0700
  • 2d93262f71 RationalCrossing: use ShiftQueues Wesley W. Terpstra 2017-09-06 14:27:45 -0700
  • 50d5d8c1fd ShiftQueue: added a helper object Wesley W. Terpstra 2017-09-06 14:26:26 -0700
  • 3e3024c256 ShiftQueue: fix bug in !flow case Wesley W. Terpstra 2017-09-06 18:15:59 -0700
  • ed70b243bd plic: support a configurable number of interrupt register stages Wesley W. Terpstra 2017-09-06 14:21:09 -0700
  • 9b55063de6 clint: support a configurable number of interrupt register stages Wesley W. Terpstra 2017-09-06 14:20:46 -0700
  • 929a924779 Merge pull request #975 from freechipsproject/async_reg Megan Wachs 2017-09-07 13:32:54 -0700
  • 1320f65ae6 Merge remote-tracking branch 'origin/master' into async_reg Megan Wachs 2017-09-07 11:27:36 -0700
  • b7acb6ca3d Merge pull request #986 from freechipsproject/jtag_vpi_reset Megan Wachs 2017-09-07 11:26:42 -0700
  • 126d56b254 synchronizers: I learn how foldRight works Megan Wachs 2017-09-07 10:46:55 -0700
  • 1da6cb85ab shiftReg: Make it so that register '0' is always closest to the q output, regardless of the type of shift register created. Megan Wachs 2017-09-07 09:51:46 -0700
  • f68390e458 jtag_vpi: Use a parameter for INIT_DELAY vs constant Megan Wachs 2017-09-07 09:06:07 -0700
  • 19eabb6728 jtag_vpi: add some hysterisis for waiting for init_done Megan Wachs 2017-09-06 18:13:04 -0700
  • dcafb5fea3 Merge remote-tracking branch 'origin/master' into async_reg Megan Wachs 2017-09-06 11:07:19 -0700
  • 3c4b472f66 shift regs: remove some unnecessary primitives, and add some that actually are necessary Megan Wachs 2017-09-06 10:37:59 -0700
  • f1b7666d21 Jtagresettobool - add explicit toBool cast now required on reset. (#984) Jim Lawson 2017-09-06 09:49:47 -0700
  • 55a0df4186 Merge pull request #982 from freechipsproject/frontbus3 Wesley W. Terpstra 2017-09-06 02:38:55 +0200
  • 777f052f95 regs: Add named/initial value ShiftRegister primitives so they are all in one place Megan Wachs 2017-09-05 17:32:53 -0700
  • b1cacc56ad SystemBus: restore correct order of FIFOFixer and Buffer Wesley W. Terpstra 2017-09-05 16:41:39 -0700
  • b74a419bfb FrontBus: FIFOFixer should not have a buffer between it and Xbar Wesley W. Terpstra 2017-09-05 16:27:57 -0700
  • e9e46db600 sync reg: Rename the file to reflect the more generic shift registers also in the file. Megan Wachs 2017-09-05 15:54:25 -0700
  • 5df23c5514 Synchronizers: remove some newlines and unncessary gen's Megan Wachs 2017-09-05 15:16:08 -0700
  • e65f49b89a FrontBus: attach to splitter for cross-chip visibility Wesley W. Terpstra 2017-09-05 15:02:16 -0700
  • 5886025b1a sbus => pbus: 2 buffers should already be enough Wesley W. Terpstra 2017-09-05 13:33:34 -0700
  • a902e15987 pbus: clarify that we are adding buffers when attaching to sbus Henry Cook 2017-09-01 18:18:13 -0700
  • 8fc4d78c84 frontbus: provide fifofixer on the side of the front bus where masters connect Henry Cook 2017-09-01 14:26:55 -0700
  • 667d966410 TLBuffer: Create a wrapper module for TLBufferChain, to allow for more stable naming Megan Wachs 2017-08-31 13:00:37 -0700
  • 94f06dc85c pbus: turn down overkill buffering between PBus and SBus Megan Wachs 2017-08-30 19:23:18 -0700
  • c353f68dc0 buses: name dummy buffers too Megan Wachs 2017-08-30 18:30:22 -0700
  • 3bde9506c6 coreplex: allow buffer chains on certain bus ports Henry Cook 2017-08-30 17:57:52 -0700
  • 57d0360c35 frontbus: Name the connection. Megan Wachs 2017-08-30 17:51:30 -0700
  • c99afe4c66 buses: Name all the things. Megan Wachs 2017-08-30 16:21:08 -0700
  • 32cb358c81 coreplex: include optional tile name for downstream name stabilization Henry Cook 2017-08-30 15:23:10 -0700
  • 183fefb2b9 Front/SystemBus: allow naming the intermediate TLNodes that get sprinkled in Megan Wachs 2017-08-30 15:27:56 -0700
  • d5b62dffda SystemBus: add stupidly many (4 more) buffers from sbus=>pbus Wesley W. Terpstra 2017-08-30 13:57:08 -0700
  • f7330028cc Add optional frontbus for peripherals mastering into SBus. Switch FF and Buffer order on non-tile masters into SBus. Buffer non-L2 side of splitter Henry Styles 2017-08-25 18:12:25 -0700
  • 173f185b17 Merge pull request #976 from freechipsproject/system-buffer Wesley W. Terpstra 2017-08-30 23:22:13 +0200
  • 656609d610 SystemBus: split FIFOFixers along bus boundaries Wesley W. Terpstra 2017-08-30 13:28:11 -0700
  • a3bc5f2e33 synchronizers: Add a generic shift register and then extend from it, since an asynchronously resettable shift register is also a useful primitive Megan Wachs 2017-08-30 12:59:16 -0700
  • 8139014c9e syncrhonizers: Remove unused sync from superclass Megan Wachs 2017-08-30 12:33:03 -0700
  • 9dd6c4c32d synchronizers: New chisel ways of cloning type and use simpler lambda function Megan Wachs 2017-08-30 12:00:14 -0700
  • bd32f0c122 synchronizers: properly pass parameters up to the superclass Megan Wachs 2017-08-30 11:58:25 -0700
  • 483e63da19 synchronizers: Correctly pass the width through Megan Wachs 2017-08-30 11:50:25 -0700
  • 91c3fa2865 Merge pull request #979 from freechipsproject/buffer_params_debuginfo Megan Wachs 2017-08-29 17:52:50 -0700
  • a62ce0afe6 TLBuffer: Add a nodedebugstring for quick browsing of the properties of the buffer. Megan Wachs 2017-08-29 10:36:46 -0700
  • c473538e36 Merge remote-tracking branch 'origin/master' into async_reg Megan Wachs 2017-08-28 17:19:03 -0700
  • 451334ac73 Add 1-deep synchronizer register for output of AsyncQueue Megan Wachs 2017-08-28 17:18:54 -0700
  • bf19440db5 SystemBus: use a full buffer on slaves Wesley W. Terpstra 2017-08-26 02:47:04 -0700
  • 85c39b2f97 syncregs: Not sure the use case for SynchronizerShiftRegInit, so remove it YAGNI Megan Wachs 2017-08-24 17:47:04 -0700
  • 4e773f4738 syncregs: Use synchronizer primivites for LevelSyncCrossing Megan Wachs 2017-08-24 17:42:31 -0700
  • 130b24355f syncregs: Use synchronizer primitives for IntXing Megan Wachs 2017-08-24 17:39:07 -0700
  • 8b462d1595 syncregs: Use common primitives for AsyncQueue grey code synchronizers Megan Wachs 2017-08-24 17:34:07 -0700
  • 3461cb47cc syncregs: Make Reset catcher use the synchronizer primitive Megan Wachs 2017-08-24 17:26:38 -0700
  • c78ee9f0e4 syncreg: Refactor common code Megan Wachs 2017-08-24 17:18:04 -0700
  • d83a6dc6af syncregs: Add utilities for Synchronizing Shift Registers Megan Wachs 2017-08-24 16:47:15 -0700
  • bdaae40035 Merge pull request #973 from freechipsproject/named_buffers Megan Wachs 2017-08-24 16:31:14 -0700
  • 7f683eeb24 async_regs: Make modules have predictable names Megan Wachs 2017-08-24 15:33:53 -0700
  • 0f75ebee92 async_reg: Rename the file to match scalastyle Megan Wachs 2017-08-24 15:31:29 -0700
  • 103b6bc6d3 systemBus: allowing naming the TLBuffers which get inserted Megan Wachs 2017-08-24 14:42:30 -0700
  • 17134125e1 SystemBus: remove misnamed functions (#972) Wesley W. Terpstra 2017-08-24 23:35:01 +0200
  • 6e689f55ed Merge pull request #965 from freechipsproject/quash_x Megan Wachs 2017-08-21 16:48:25 -0700
  • 81890e3a42 async_reg: Clean up some funky indentation Megan Wachs 2017-08-21 16:06:36 -0700
  • 4f45379863 async_reset_reg: Squash X's the same as for reset reg Megan Wachs 2017-08-21 14:33:19 -0700
  • 82df766f4a Merge pull request #963 from freechipsproject/interrupt-order Andrew Waterman 2017-08-18 00:10:19 -0700
  • 8087a205cc Remove redundant check in interrupt priority encoding Andrew Waterman 2017-08-17 22:23:42 -0700
  • cbe7c51b50 Respect ISA requirements on interrupt priority order Andrew Waterman 2017-08-17 21:27:08 -0700
  • b1719cfee0 Fixing requirements for PAddrBits (#961) Shreesha Srinath 2017-08-17 11:53:59 -0700
  • 1db4b3be9a Merge pull request #957 from freechipsproject/param_jtag_vpi Megan Wachs 2017-08-14 18:37:30 -0700
  • 8783d51c97 jtag_vpi: Use Parameterized Black Box to allow TestHarnesses to override the clock speed Megan Wachs 2017-08-14 17:25:47 -0700
  • 710a782145 HeterogenousBag: empty bags were being combined! (#956) Wesley W. Terpstra 2017-08-14 15:48:42 -0700
  • e945f6e265 Merge pull request #955 from freechipsproject/fix-acquire-before-release Andrew Waterman 2017-08-13 18:29:58 -0700
  • 57a5965bf4 Merge pull request #954 from freechipsproject/max-core-cycles Megan Wachs 2017-08-13 16:45:59 -0700
  • 88332bd885 max-core-cycles: Add a +max-core-cycles PlusArg Megan Wachs 2017-08-13 15:20:47 -0700
  • 3cbc5262ec Don't permit new acquires until the release queue is drained Andrew Waterman 2017-08-13 13:03:45 -0700
  • 0190724492 Actually use the C-channel acquire-before-release queue Andrew Waterman 2017-08-13 12:23:16 -0700
  • 41a2a03f90 Merge pull request #953 from freechipsproject/fix-dcache-ecc Andrew Waterman 2017-08-12 16:47:19 -0700
  • 7387f2a93a Don't block D-channel when handling a probe Andrew Waterman 2017-08-12 16:13:24 -0700
  • 604abd5b07 Only report ECC errors when the RAM was actually read Andrew Waterman 2017-08-12 15:28:03 -0700
  • 18fb052fc9 DRY Andrew Waterman 2017-08-12 15:27:30 -0700
  • 176110b6d3 Don't trigger ECC writebacks when a release is in flight Andrew Waterman 2017-08-12 15:23:57 -0700