riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Commit Graph

  • 9307092d14 coreplex: draw the FrontBus at the bottom and SystemBus at the top Wesley W. Terpstra 2017-09-27 14:20:39 -0700
  • f48bf2ac2f rocket: connect uncrossed output interrupts Henry Cook 2017-09-27 12:53:19 -0700
  • 78f3877e02 Trace tval field should be zero when not taking exceptions Andrew Waterman 2017-09-27 12:51:10 -0700
  • e07d86aecd rocket: flip interrupt rendering so cores are on top Wesley W. Terpstra 2017-09-27 12:46:29 -0700
  • 583adeee88 Separate interrupt bit from cause field in trace bundle Andrew Waterman 2017-09-27 12:41:30 -0700
  • 1fda05970a rocket: move interrupt synchronizers to correct side of crossing Wesley W. Terpstra 2017-09-27 12:02:04 -0700
  • ce01ab2700 RegisterRouter: correctly create interrupts vector Wesley W. Terpstra 2017-09-27 12:27:16 -0700
  • 0268959c24 rocket: move interrupt synchronizers to correct side of crossing Wesley W. Terpstra 2017-09-27 12:02:04 -0700
  • e35d3df6ea diplomacy: detect and report cycles in the diplomatic graph Wesley W. Terpstra 2017-09-27 11:46:06 -0700
  • 5af08966d8 coreplex: fix WithoutTLMonitors Wesley W. Terpstra 2017-09-27 00:57:18 -0700
  • d87536ff8b diplomacy: make NodeHandle recursively composable Wesley W. Terpstra 2017-09-26 18:47:16 -0700
  • 31a934bec0 coreplex: buses are now LazyModules with LazyScope Wesley W. Terpstra 2017-09-26 14:58:18 -0700
  • da40573a64 diplomacy: replace LazyModule.stack with an optional scope Wesley W. Terpstra 2017-09-26 14:56:50 -0700
  • a2b423d647 diplomacy: add LazyScope to post-hoc add children to a LazyModule Wesley W. Terpstra 2017-09-26 14:40:45 -0700
  • a27e853101 diplomacy: move rendering properties to edges Wesley W. Terpstra 2017-09-26 13:23:54 -0700
  • 76c2aa1661 diplomacy: introduce the typing-saving SimpleNodeImp Wesley W. Terpstra 2017-09-26 12:28:59 -0700
  • 870ed3d219 diplomacy: fix the order of auto signals Wesley W. Terpstra 2017-09-25 18:09:03 -0700
  • d22ec1eddf diplomacy: beautify node signal prefixes Wesley W. Terpstra 2017-09-25 17:49:45 -0700
  • 45d26ea130 Merge pull request #1015 from freechipsproject/coherence-manager Henry Cook 2017-09-26 11:09:48 -0700
  • 9d5e96672e coreplex: clean up coherence manager attachment point Henry Cook 2017-09-25 17:51:35 -0700
  • 0111213bea ValName: trim whitespace from symbol names Wesley W. Terpstra 2017-09-25 17:47:40 -0700
  • fef5054cec diplomacy: disambiguate names only when necessary Wesley W. Terpstra 2017-09-25 16:12:34 -0700
  • a86a9c5564 Fix omitted parameter (#1014) pbing 2017-09-25 23:11:28 +0200
  • 5323cf88dd util: add Option.unzip Wesley W. Terpstra 2017-09-25 11:25:46 -0700
  • 60614055e3 diplomacy: eliminate some wasted IdentityNodes using cross-module refs Wesley W. Terpstra 2017-09-23 00:04:50 -0700
  • bc225a4e82 diplomacy: place Monitors inside LazyModules sinks Wesley W. Terpstra 2017-09-22 16:55:12 -0700
  • cfb7f13408 diplomacy: capture SourceInfo at point of := in Edge parameters Wesley W. Terpstra 2017-09-22 22:23:58 -0700
  • 16969eb1f6 diplomacy: spelling fix Wesley W. Terpstra 2017-09-22 14:57:36 -0700
  • b9a2e4c243 diplomacy: API beautification Wesley W. Terpstra 2017-09-15 14:44:07 -0700
  • 9217baf9d4 diplomacy: change API to auto-create node bundles => cross-module refs Wesley W. Terpstra 2017-09-13 18:06:03 -0700
  • 53f6999ea8 Splitter: reuse TLCustom node instead of special diplomacy case Wesley W. Terpstra 2017-09-13 13:44:06 -0700
  • 6fa5250e1f config: fix warning Wesley W. Terpstra 2017-09-12 12:22:47 -0700
  • 17ba209ed0 coreplex: name LazyModules Wesley W. Terpstra 2017-09-12 12:16:28 -0700
  • 1fedabcb55 tilelink: invoke LazyModule() at point of monitor binding Wesley W. Terpstra 2017-09-12 12:12:49 -0700
  • dfc815f4d3 rocket: invoke LazyModule at point of use/binding Wesley W. Terpstra 2017-09-12 12:10:39 -0700
  • 87d597c70d ahb apb: remove unintentional var Wesley W. Terpstra 2017-09-12 12:09:58 -0700
  • d89ee9d9d4 nodes: grab a name on construction Wesley W. Terpstra 2017-09-11 23:33:44 -0700
  • 3656e975a1 diplomacy: ValName captures val bindings for Nodes Wesley W. Terpstra 2017-09-11 19:31:44 -0700
  • 5662d1de0b Merge pull request #1012 from freechipsproject/halt-and-catch-fire Henry Cook 2017-09-22 09:30:30 -0700
  • 81e136aa37 rocket: give l2 tlb a nice name Henry Cook 2017-09-21 18:13:39 -0700
  • 30c8c8c517 Revert "try to give seqmems clearer names" Henry Cook 2017-09-21 18:02:32 -0700
  • e0b9f9213a make halt_and_catch_fire Optional Henry Cook 2017-09-21 14:58:15 -0700
  • 28b635e721 tile: add halt_and_catch_fire signal Henry Cook 2017-09-20 18:53:44 -0700
  • a887baa615 rocket: base trait for reporting ecc errors Henry Cook 2017-09-20 18:49:46 -0700
  • ffa3ab29ac Merge pull request #1006 from freechipsproject/async_reset_reg Megan Wachs 2017-09-21 11:48:04 -0700
  • 4f58aab26f Bumpplugins - add sbt-coverage (#1004) Jim Lawson 2017-09-20 17:17:55 -0700
  • 88c782cc70 Report D$ uncorrectable errors on C channel Andrew Waterman 2017-09-20 17:15:00 -0700
  • 6bc20942b5 Don't cache TL error responses; report access exceptions Andrew Waterman 2017-09-20 17:01:08 -0700
  • 323a207bdd Merge pull request #1005 from freechipsproject/trace Henry Cook 2017-09-20 15:34:45 -0700
  • 9b828a2640 Only look at error signal on last beat Andrew Waterman 2017-09-20 15:15:21 -0700
  • cda89fbacb async_reset_reg: Don't randomize the register if rst is asserted anyway Megan Wachs 2017-09-20 14:47:00 -0700
  • 026fa14bf8 Rename trace.addr -> iaddr Andrew Waterman 2017-09-20 14:32:41 -0700
  • 1cb91eed41 Merge pull request #1003 from freechipsproject/ma-fetch Henry Cook 2017-09-20 14:28:26 -0700
  • 5b2f458214 Merge branch 'master' into ma-fetch Andrew Waterman 2017-09-20 12:18:03 -0700
  • f1a506476b Merge pull request #994 from freechipsproject/beu Andrew Waterman 2017-09-20 12:17:08 -0700
  • 00cf089350 Merge pull request #1002 from freechipsproject/trace Henry Cook 2017-09-20 11:50:40 -0700
  • f5bd639863 Don't write badaddr on misaligned fetch exceptions Andrew Waterman 2017-09-20 10:52:41 -0700
  • db57e943f3 Report TL errors into D$ Andrew Waterman 2017-09-20 00:04:33 -0700
  • aaad73f019 Add an intra-tile xbar Andrew Waterman 2017-09-19 17:49:27 -0700
  • afad25fceb Integrate L1 BusErrorUnit Andrew Waterman 2017-09-15 18:49:40 -0700
  • dbf599f6a1 Support SynchronizerShiftReg(sync = 0) Andrew Waterman 2017-09-19 12:05:00 -0700
  • 79dab487fc Implement bus error unit Andrew Waterman 2017-09-15 18:46:19 -0700
  • ed18acaae0 Report D$ errors Andrew Waterman 2017-09-15 18:41:19 -0700
  • 034ea722f4 Report I$ errors Andrew Waterman 2017-09-15 18:41:50 -0700
  • 9a175b0fb1 Statically report error correction/detection capability from ECC codes Andrew Waterman 2017-09-15 18:44:55 -0700
  • 4d6d6ff641 Add instruction-trace port Andrew Waterman 2017-09-19 22:59:28 -0700
  • acea94bcef Merge pull request #1001 from freechipsproject/address-decoder Andrew Waterman 2017-09-19 22:38:53 -0700
  • b4fc5104d4 Add cover property API that can be refined through Config PropertyLibrary (#998) Jacob Chang 2017-09-19 19:26:54 -0700
  • 57e8fe0a6b Merge pull request #1000 from freechipsproject/name-seqmems Henry Cook 2017-09-19 17:59:00 -0700
  • 87b92cb206 Scan AddressDecoder bits left to right Andrew Waterman 2017-09-19 17:46:18 -0700
  • 72bd89a2af Add another AddressDecoder debug message Andrew Waterman 2017-09-19 17:46:04 -0700
  • fb2ad11347 Improve AddressDecoder optimization function Andrew Waterman 2017-09-19 17:45:10 -0700
  • 8db5bbbae0 try to give seqmems clearer names Henry Cook 2017-09-19 13:41:11 -0700
  • cbd65cd247 Merge pull request #992 from freechipsproject/test_mode_reset Megan Wachs 2017-09-18 14:16:49 -0700
  • 528deefdc7 Change SystemVerilog statement into standard Verilog (#997) pbing 2017-09-18 19:57:07 +0200
  • 826fc8ba61 Merge remote-tracking branch 'origin/master' into test_mode_reset Megan Wachs 2017-09-18 09:50:27 -0700
  • c24b275fd9 Merge pull request #996 from freechipsproject/fix-dcache-bug Yunsup Lee 2017-09-17 15:59:32 -0700
  • d93d7b9fa4 Only merge stores that aren't yet pending Andrew Waterman 2017-09-17 14:59:09 -0700
  • c85333f826 Merge remote-tracking branch 'origin/test_mode_reset' into test_mode_reset Megan Wachs 2017-09-17 13:51:46 -0700
  • 215e072e5c test_mode_reset: fix typos Megan Wachs 2017-09-17 13:51:40 -0700
  • 9b75dd7e5b Merge branch 'master' into test_mode_reset Henry Cook 2017-09-15 17:26:11 -0700
  • 641a8e7eab test_mode_reset: Correct some gender issues. Tie off signals in the test harness Megan Wachs 2017-09-15 16:36:35 -0700
  • e8702e2687 Merge pull request #989 from freechipsproject/config-cleanups Henry Cook 2017-09-15 13:45:15 -0700
  • 6cda4504ac test_mode_reset: use a cleaner interface with bundles and options instead of individual signals Megan Wachs 2017-09-15 12:30:39 -0700
  • ffc514d1bc test_mode_reset: Add missing file Megan Wachs 2017-09-14 13:17:37 -0700
  • a0396b63e8 test_mode_reset: fix one bulk-connect gender issue Megan Wachs 2017-09-14 13:15:24 -0700
  • 44edc5fdc3 test_mode_reset: Use simpler apply() method Megan Wachs 2017-09-13 17:00:01 -0700
  • 82c00cb656 reset_catch: Allow Test Mode Overrides Megan Wachs 2017-09-12 16:05:13 -0700
  • e50d14415e tilelink: more verbose requires Henry Cook 2017-09-12 17:35:28 -0700
  • 56dae946b6 coreplex: MemoryBusParams.beatBytes also based on XLen Henry Cook 2017-09-08 19:08:53 -0700
  • b86f4b9bb7 config: use Field defaults over Config defaults Henry Cook 2017-09-08 18:33:44 -0700
  • a7540d35b7 ports: use BigInts instead of Longs and the new x"..." context Henry Cook 2017-09-08 16:21:05 -0700
  • 37c5af1c0d diplomacy: add x"..." string context Henry Cook 2017-09-08 16:17:45 -0700
  • 063ca0ed4a Merge pull request #983 from freechipsproject/kill-paddrbits Henry Cook 2017-09-11 12:51:10 -0700
  • 1f606d924f Don't perform in-place correction if there was a recent store (#988) Andrew Waterman 2017-09-08 16:26:54 -0700
  • 9c0bfbd500 tile: remove global Field ResetVectorBits Henry Cook 2017-09-01 17:50:54 -0700
  • 3133c321b7 scratchpad: remove dependency on HasCoreParameters Henry Cook 2017-08-31 19:07:08 -0700
  • e46aeb7342 tile: remove PAddrBits in favor of SharedMemoryTLEdge Henry Cook 2017-08-31 18:48:59 -0700
  • e7de7f3e82 Merge pull request #985 from freechipsproject/flop-interrupts Wesley W. Terpstra 2017-09-08 13:16:11 -0700
  • 53dfc5e9be Remove overzealous assertion (#987) Andrew Waterman 2017-09-07 18:17:56 -0700