riscv/rocket-chip
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rocket: move interrupt synchronizers to correct side of crossing

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This commit is contained in:
Wesley W. Terpstra
2017-09-27 12:02:04 -07:00
committed by Henry Cook
parent 45d26ea130
commit 1fda05970a
2 changed files with 5 additions and 7 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@@ -84,7 +84,11 @@ trait HasRocketTiles extends HasSystemBus
lip.foreach { coreIntXbar.intnode := _ } // lip
wrapper.coreIntNode := coreIntXbar.intnode
wrapper.intOutputNode.foreach { plic.intnode := _ }
wrapper.intOutputNode.foreach { case int =>
val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
rocketIntXing.intnode := int
plic.intnode := rocketIntXing.intnode
}
wrapper
}

6
src/main/scala/tile/RocketTile.scala
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@@ -213,12 +213,6 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
def outputInterruptXingLatency: Int
rocket.intOutputNode.foreach { rocketIntOutputNode =>
val outXing = LazyModule(new IntXing(outputInterruptXingLatency))
intOutputNode.get := outXing.intnode
outXing.intnode := rocketIntOutputNode
}
lazy val module = new LazyModuleImp(this) {
val io = new CoreBundle
with HasExternallyDrivenTileConstants