1
0
Fork 0

rocket: flip interrupt rendering so cores are on top

This commit is contained in:
Wesley W. Terpstra 2017-09-27 12:46:29 -07:00
parent ce01ab2700
commit e07d86aecd
1 changed files with 1 additions and 1 deletions

View File

@ -86,7 +86,7 @@ trait HasRocketTiles extends HasSystemBus
wrapper.intOutputNode.foreach { case int =>
val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
rocketIntXing.intnode := int
FlipRendering { implicit p => rocketIntXing.intnode := int }
plic.intnode := rocketIntXing.intnode
}