1
0

Change SystemVerilog statement into standard Verilog (#997)

This commit is contained in:
pbing 2017-09-18 19:57:07 +02:00 committed by Andrew Waterman
parent c24b275fd9
commit 528deefdc7

View File

@ -30,7 +30,7 @@ module {name}(
initial begin
`ifdef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
for (i = 0; i < {depth}; i++) begin
for (i = 0; i < {depth}; i = i + 1) begin
rom[i] = {{{num_random_blocks}{{$random}}}};
end
`endif