Merge pull request #989 from freechipsproject/config-cleanups
Clean up various Configs/Fields/Params
This commit is contained in:
commit
e8702e2687
@ -5,7 +5,7 @@ package freechips.rocketchip.config
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abstract class Field[T] private (val default: Option[T])
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{
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def this() = this(None)
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def this(x: T) = this(Some(x))
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def this(default: T) = this(Some(default))
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}
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abstract class View {
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@ -16,25 +16,17 @@ import freechips.rocketchip.util._
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class BaseCoreplexConfig extends Config ((site, here, up) => {
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// Tile parameters
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case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
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case ASIdBits => 0
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case XLen => 64 // Applies to all cores
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case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
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case BuildCore => (p: Parameters) => new Rocket()(p)
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case RocketTilesKey => Nil // Will be added by partial configs found below
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// Interconnect parameters
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case RocketCrossing => SynchronousCrossing()
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case BroadcastParams => BroadcastParams()
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case BankedL2Params => BankedL2Params()
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case SystemBusParams => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case PeripheryBusParams => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case MemoryBusParams => MemoryBusParams(beatBytes = 8, blockBytes = site(CacheBlockBytes))
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case CacheBlockBytes => 64
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// Device parameters
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case SystemBusKey => SystemBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
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// Additional device Parameters
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case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
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case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
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case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
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case PLICParams => PLICParams()
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case ClintParams => ClintParams()
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case DTSTimebase => BigInt(1000000) // 1 MHz
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case TLBusDelayProbability => 0.0
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})
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/* Composable partial function Configs to set individual parameters */
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@ -47,11 +39,11 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
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mulEarlyOut = true,
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divEarlyOut = true))),
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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blockBytes = site(CacheBlockBytes))))
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List.fill(n)(big) ++ up(RocketTilesKey, site)
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}
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@ -63,14 +55,14 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
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core = RocketCoreParams(useVM = false, fpu = None),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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nMSHRs = 0,
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blockBytes = site(CacheBlockBytes))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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@ -89,7 +81,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
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mulDiv = Some(MulDivParams(mulUnroll = 8))),
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btb = None,
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dcache = Some(DCacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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nSets = 256, // 16Kb scratchpad
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nWays = 1,
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nTLBEntries = 4,
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@ -97,7 +89,7 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
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blockBytes = site(CacheBlockBytes),
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scratch = Some(0x80000000L))),
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icache = Some(ICacheParams(
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rowBits = site(SystemBusParams).beatBits,
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rowBits = site(SystemBusKey).beatBits,
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nSets = 64,
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nWays = 1,
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nTLBEntries = 4,
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@ -107,11 +99,11 @@ class WithNTinyCores(n: Int) extends Config((site, here, up) => {
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})
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class WithNBanksPerMemChannel(n: Int) extends Config((site, here, up) => {
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case BankedL2Params => up(BankedL2Params, site).copy(nBanksPerChannel = n)
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case BankedL2Key => up(BankedL2Key, site).copy(nBanksPerChannel = n)
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})
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class WithNTrackersPerBank(n: Int) extends Config((site, here, up) => {
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case BroadcastParams => up(BroadcastParams, site).copy(nTrackers = n)
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case BroadcastKey => up(BroadcastKey, site).copy(nTrackers = n)
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})
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// This is the number of icache sets for all Rocket tiles
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@ -143,7 +135,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config((site, here, up) => {
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})
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class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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case BroadcastParams => up(BroadcastParams, site).copy(bufferless = true)
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case BroadcastKey => up(BroadcastKey, site).copy(bufferless = true)
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})
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/**
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@ -159,7 +151,7 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
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* DO NOT use this configuration.
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*/
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class WithStatelessBridge extends Config((site, here, up) => {
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case BankedL2Params => up(BankedL2Params, site).copy(coherenceManager = { case (q, _) =>
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case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { case (q, _) =>
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implicit val p = q
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val cork = LazyModule(new TLCacheCork(unsafe = true))
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(cork.node, cork.node)
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@ -253,7 +245,7 @@ class WithRationalRocketTiles extends Config((site, here, up) => {
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})
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class WithEdgeDataBits(dataBits: Int) extends Config((site, here, up) => {
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case MemoryBusParams => up(MemoryBusParams, site).copy(beatBytes = dataBits/8)
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case MemoryBusKey => up(MemoryBusKey, site).copy(beatBytes = dataBits/8)
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case ExtIn => up(ExtIn, site).copy(beatBytes = dataBits/8)
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})
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@ -263,11 +255,11 @@ class WithJtagDTM extends Config ((site, here, up) => {
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})
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class WithNoPeripheryArithAMO extends Config ((site, here, up) => {
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case PeripheryBusParams => up(PeripheryBusParams, site).copy(arithmetic = false)
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(arithmetic = false)
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})
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class WithNBitPeripheryBus(nBits: Int) extends Config ((site, here, up) => {
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case PeripheryBusParams => up(PeripheryBusParams, site).copy(beatBytes = nBits/8)
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(beatBytes = nBits/8)
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})
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class WithoutTLMonitors extends Config ((site, here, up) => {
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@ -279,7 +271,7 @@ class WithNExtTopInterrupts(nExtInts: Int) extends Config((site, here, up) => {
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})
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class WithNMemoryChannels(n: Int) extends Config((site, here, up) => {
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case BankedL2Params => up(BankedL2Params, site).copy(nMemoryChannels = n)
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case BankedL2Key => up(BankedL2Key, site).copy(nMemoryChannels = n)
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})
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class WithExtMemSize(n: Long) extends Config((site, here, up) => {
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@ -15,7 +15,7 @@ case class FrontBusParams(
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slaveBuffering: BufferParams = BufferParams.default
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) extends TLBusParams
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case object FrontBusParams extends Field[FrontBusParams]
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case object FrontBusKey extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
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@ -50,7 +50,7 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasFrontBus extends HasSystemBus {
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private val frontbusParams = p(FrontBusParams)
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private val frontbusParams = p(FrontBusKey)
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val frontbusBeatBytes = frontbusParams.beatBytes
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val fbus = new FrontBus(frontbusParams)
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@ -30,7 +30,7 @@ trait HasInterruptBus {
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}
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/** Specifies the number of external interrupts */
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case object NExtTopInterrupts extends Field[Int]
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case object NExtTopInterrupts extends Field[Int](0)
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/** This trait adds externally driven interrupts to the system.
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* However, it should not be used directly; instead one of the below
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@ -9,13 +9,14 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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// TODO: applies to all caches, for now
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case object CacheBlockBytes extends Field[Int]
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case object CacheBlockBytes extends Field[Int](64)
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/** L2 Broadcast Hub configuration */
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case class BroadcastParams(
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nTrackers: Int = 4,
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bufferless: Boolean = false)
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case object BroadcastParams extends Field[BroadcastParams]
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case object BroadcastKey extends Field(BroadcastParams())
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/** L2 memory subsystem configuration */
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case class BankedL2Params(
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@ -23,14 +24,15 @@ case class BankedL2Params(
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nBanksPerChannel: Int = 1,
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coherenceManager: (Parameters, HasMemoryBus) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
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implicit val p = q
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val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusParams)
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val BroadcastParams(nTrackers, bufferless) = p(BroadcastParams)
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val MemoryBusParams(_, blockBytes, _, _) = p(MemoryBusKey)
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val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
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val bh = LazyModule(new TLBroadcast(blockBytes, nTrackers, bufferless))
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(bh.node, bh.node)
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}) {
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val nBanks = nMemoryChannels*nBanksPerChannel
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}
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case object BankedL2Params extends Field[BankedL2Params]
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case object BankedL2Key extends Field(BankedL2Params())
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/** Parameterization of the memory-side bus created for each memory channel */
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case class MemoryBusParams(
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@ -40,7 +42,7 @@ case class MemoryBusParams(
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slaveBuffering: BufferParams = BufferParams.none
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) extends TLBusParams
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case object MemoryBusParams extends Field[MemoryBusParams]
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case object MemoryBusKey extends Field[MemoryBusParams]
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/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
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class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "MemoryBus")(p) {
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@ -50,9 +52,9 @@ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWr
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}
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trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBus {
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private val mbusParams = p(MemoryBusParams)
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private val mbusParams = p(MemoryBusKey)
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private val MemoryBusParams(beatBytes, blockBytes, _, _) = mbusParams
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private val l2Params = p(BankedL2Params)
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private val l2Params = p(BankedL2Key)
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val BankedL2Params(nMemoryChannels, nBanksPerChannel, coherenceManager) = l2Params
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val nBanks = l2Params.nBanks
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val cacheBlockBytes = blockBytes
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@ -19,7 +19,7 @@ case class PeripheryBusParams(
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) extends TLBusParams {
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}
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case object PeripheryBusParams extends Field[PeripheryBusParams]
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case object PeripheryBusKey extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
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@ -42,7 +42,7 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasPeripheryBus extends HasSystemBus {
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private val pbusParams = p(PeripheryBusParams)
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private val pbusParams = p(PeripheryBusKey)
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val pbusBeatBytes = pbusParams.beatBytes
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val pbus = new PeripheryBus(pbusParams)
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@ -11,8 +11,8 @@ import freechips.rocketchip.util._
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/** Specifies the size and width of external memory ports */
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case class MasterPortParams(
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base: Long,
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size: Long,
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base: BigInt,
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size: BigInt,
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beatBytes: Int,
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idBits: Int,
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maxXferBytes: Int = 256,
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@ -86,7 +86,7 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
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private val device = new SimpleBus("mmio", Nil)
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val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = List(AddressSet(BigInt(params.base), params.size-1)),
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address = List(AddressSet(params.base, params.size-1)),
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resources = device.ranges,
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executable = params.executable,
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supportsWrite = TransferSizes(1, params.maxXferBytes),
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@ -162,7 +162,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
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private val device = new SimpleBus("mmio", Nil)
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val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
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managers = Seq(TLManagerParameters(
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address = List(AddressSet(BigInt(params.base), params.size-1)),
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address = List(AddressSet(params.base, params.size-1)),
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resources = device.ranges,
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executable = params.executable,
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supportsGet = TransferSizes(1, sbus.blockBytes),
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@ -237,7 +237,7 @@ trait HasSlaveTLPortModuleImp extends LazyMultiIOModuleImp with HasSlaveTLPortBu
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/** Memory with AXI port for use in elaboratable test harnesses. */
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class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) extends LazyModule {
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val config = p(ExtMem)
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val totalSize = if (forceSize > 0) forceSize else BigInt(config.size)
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val totalSize = if (forceSize > 0) forceSize else config.size
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val size = totalSize / channels
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require(totalSize % channels == 0)
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@ -8,7 +8,7 @@ import freechips.rocketchip.devices.tilelink.HasPeripheryClint
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trait HasRTCModuleImp extends LazyMultiIOModuleImp {
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val outer: HasPeripheryClint
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private val pbusFreq = outer.p(PeripheryBusParams).frequency
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private val pbusFreq = outer.p(PeripheryBusKey).frequency
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private val rtcFreq = outer.p(DTSTimebase)
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private val internalPeriod: BigInt = pbusFreq / rtcFreq
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@ -11,8 +11,8 @@ import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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case object RocketTilesKey extends Field[Seq[RocketTileParams]]
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case object RocketCrossing extends Field[CoreplexClockCrossing]
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case object RocketTilesKey extends Field[Seq[RocketTileParams]](Nil)
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case object RocketCrossing extends Field[CoreplexClockCrossing](SynchronousCrossing())
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trait HasRocketTiles extends HasSystemBus
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with HasPeripheryBus
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@ -15,7 +15,7 @@ case class SystemBusParams(
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slaveBuffering: BufferParams = BufferParams.default
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) extends TLBusParams
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case object SystemBusParams extends Field[SystemBusParams]
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case object SystemBusKey extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "SystemBus") {
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@ -119,7 +119,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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* for use in traits that connect individual devices or external ports.
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*/
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trait HasSystemBus extends HasInterruptBus {
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private val sbusParams = p(SystemBusParams)
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private val sbusParams = p(SystemBusKey)
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val sbusBeatBytes = sbusParams.beatBytes
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val sbus = new SystemBus(sbusParams)
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@ -19,7 +19,7 @@ case class JtagDTMConfig (
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// the lines of p(JtagDTMKey).idcodeManufId.U(11.W).
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debugIdleCycles : Int)
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case object JtagDTMKey extends Field[JtagDTMConfig]
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case object JtagDTMKey extends Field[JtagDTMConfig](new JtagDTMKeyDefault())
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class JtagDTMKeyDefault extends JtagDTMConfig(
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idcodeVersion = 0,
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@ -12,7 +12,7 @@ import freechips.rocketchip.jtag._
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import freechips.rocketchip.util._
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/** A knob selecting one of the two possible debug interfaces */
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case object IncludeJtagDTM extends Field[Boolean]
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case object IncludeJtagDTM extends Field[Boolean](false)
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/** A wrapper bundle containing one of the two possible debug interfaces */
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class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
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@ -30,7 +30,7 @@ case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
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def address = AddressSet(baseAddress, ClintConsts.size-1)
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}
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case object ClintParams extends Field[ClintParams]
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case object ClintKey extends Field(ClintParams())
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class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) extends LazyModule
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{
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@ -96,6 +96,6 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
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/** Trait that will connect a Clint to a coreplex */
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trait HasPeripheryClint extends HasPeripheryBus {
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val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintParams)))
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val clint = LazyModule(new CoreplexLocalInterrupter(p(ClintKey)))
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clint.node := pbus.toVariableWidthSlaves
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}
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@ -58,7 +58,7 @@ case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7, i
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def address = AddressSet(baseAddress, PLICConsts.size-1)
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}
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case object PLICParams extends Field[PLICParams]
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case object PLICKey extends Field(PLICParams())
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/** Platform-Level Interrupt Controller */
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class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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@ -238,7 +238,7 @@ class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
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/** Trait that will connect a PLIC to a coreplex */
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trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
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val plic = LazyModule(new TLPLIC(p(PLICParams)))
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val plic = LazyModule(new TLPLIC(p(PLICKey)))
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plic.node := pbus.toVariableWidthSlaves
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plic.intnode := ibus.toPLIC
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}
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@ -8,7 +8,7 @@ import java.io.{ByteArrayInputStream, ByteArrayOutputStream}
|
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|
||||
case object DTSModel extends Field[String]
|
||||
case object DTSCompat extends Field[Seq[String]] // -dev, -soc
|
||||
case object DTSTimebase extends Field[BigInt] // Clock frequency of clint RTC (use 0 if you don't know it)
|
||||
case object DTSTimebase extends Field[BigInt](0) // Clock frequency of clint RTC (use 0 if you don't know it)
|
||||
|
||||
object DTS
|
||||
{
|
||||
|
@ -22,6 +22,13 @@ package object diplomacy
|
||||
}
|
||||
}
|
||||
|
||||
implicit class BigIntHexContext(val sc: StringContext) extends AnyVal {
|
||||
def x(args: Any*): BigInt = {
|
||||
val orig = sc.s(args: _*)
|
||||
BigInt(orig.replace("_", ""), 16)
|
||||
}
|
||||
}
|
||||
|
||||
def SinkCardinality[T](body: Parameters => T)(implicit p: Parameters) = body(p.alterPartial {
|
||||
case CardinalityInferenceDirectionKey => CardinalityInferenceDirection.SINK_TO_SOURCE
|
||||
})
|
||||
|
@ -25,8 +25,8 @@ class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) extends Config(
|
||||
addrBag = {
|
||||
val nSets = 2
|
||||
val nWays = 1
|
||||
val blockOffset = site(SystemBusParams).blockOffset
|
||||
val nBeats = site(SystemBusParams).blockBeats
|
||||
val blockOffset = site(SystemBusKey).blockOffset
|
||||
val nBeats = site(SystemBusKey).blockBeats
|
||||
List.tabulate(4 * nWays) { i =>
|
||||
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
|
||||
}.flatten
|
||||
|
@ -13,8 +13,8 @@ import freechips.rocketchip.tile.{XLen, CoreModule, CoreBundle}
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.util._
|
||||
|
||||
case object PgLevels extends Field[Int]
|
||||
case object ASIdBits extends Field[Int]
|
||||
case object PgLevels extends Field[Int](2)
|
||||
case object ASIdBits extends Field[Int](0)
|
||||
|
||||
class SFenceReq(implicit p: Parameters) extends CoreBundle()(p) {
|
||||
val rs1 = Bool()
|
||||
|
@ -6,32 +6,27 @@ package freechips.rocketchip.system
|
||||
import Chisel._
|
||||
import freechips.rocketchip.config.Config
|
||||
import freechips.rocketchip.coreplex._
|
||||
import freechips.rocketchip.devices.debug._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => {
|
||||
// DTS descriptive parameters
|
||||
case DTSModel => "freechips,rocketchip-unknown"
|
||||
case DTSCompat => Nil
|
||||
case DTSTimebase => BigInt(1000000) // 1 MHz
|
||||
// External port parameters
|
||||
case IncludeJtagDTM => false
|
||||
case JtagDTMKey => new JtagDTMKeyDefault()
|
||||
case NExtTopInterrupts => 2
|
||||
case ExtMem => MasterPortParams(
|
||||
base = 0x80000000L,
|
||||
size = 0x10000000L,
|
||||
beatBytes = site(MemoryBusParams).beatBytes,
|
||||
base = x"8000_0000",
|
||||
size = x"1000_0000",
|
||||
beatBytes = site(MemoryBusKey).beatBytes,
|
||||
idBits = 4)
|
||||
case ExtBus => MasterPortParams(
|
||||
base = 0x60000000L,
|
||||
size = 0x20000000L,
|
||||
beatBytes = site(MemoryBusParams).beatBytes,
|
||||
base = x"6000_0000",
|
||||
size = x"2000_0000",
|
||||
beatBytes = site(MemoryBusKey).beatBytes,
|
||||
idBits = 4)
|
||||
case ExtIn => SlavePortParams(beatBytes = 8, idBits = 8, sourceBits = 4)
|
||||
// Additional device Parameters
|
||||
case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
|
||||
case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
|
||||
}))
|
||||
|
||||
class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
|
||||
|
@ -6,7 +6,7 @@ import Chisel._
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
|
||||
case object TLBusDelayProbability extends Field[Double]
|
||||
case object TLBusDelayProbability extends Field[Double](0.0)
|
||||
|
||||
/** Specifies widths of various attachement points in the SoC */
|
||||
trait TLBusParams {
|
||||
|
@ -66,8 +66,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
|
||||
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
|
||||
require (manager.endSinkId <= 1)
|
||||
|
||||
// We don't support fragmenting to sub-beat accesses
|
||||
require (minSize >= beatBytes)
|
||||
require (minSize >= beatBytes, s"We don't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
|
||||
// We can't support devices which are cached on both sides of us
|
||||
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
|
||||
|
||||
|
@ -30,12 +30,12 @@ case class TLManagerParameters(
|
||||
address.foreach { a => require (a.finite) }
|
||||
|
||||
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
|
||||
require (supportsPutFull.contains(supportsPutPartial))
|
||||
require (supportsPutFull.contains(supportsArithmetic))
|
||||
require (supportsPutFull.contains(supportsLogical))
|
||||
require (supportsGet.contains(supportsArithmetic))
|
||||
require (supportsGet.contains(supportsLogical))
|
||||
require (supportsAcquireB.contains(supportsAcquireT))
|
||||
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
|
||||
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
|
||||
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
|
||||
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
|
||||
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
|
||||
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
|
||||
|
||||
// Make sure that the regionType agrees with the capabilities
|
||||
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
|
||||
|
Loading…
Reference in New Issue
Block a user