Merge pull request #1002 from freechipsproject/trace
Add instruction-trace port
This commit is contained in:
commit
00cf089350
@ -65,6 +65,7 @@ case class TraceGenParams(
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memStart: BigInt, //p(ExtMem).base
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numGens: Int) extends GroundTestTileParams {
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def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
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val trace = false
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}
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trait HasTraceGenParams {
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@ -149,6 +149,16 @@ class PerfCounterIO(implicit p: Parameters) extends CoreBundle
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val inc = UInt(INPUT, log2Ceil(1+retireWidth))
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}
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class TracedInstruction(implicit p: Parameters) extends CoreBundle {
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val valid = Bool()
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val addr = UInt(width = coreMaxAddrBits)
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val insn = UInt(width = iLen)
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val priv = UInt(width = 3)
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val exception = Bool()
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val cause = UInt(width = 1 + log2Ceil(xLen))
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val tval = UInt(width = coreMaxAddrBits max iLen)
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}
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class CSRFileIO(implicit p: Parameters) extends CoreBundle
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with HasRocketCoreParameters {
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val interrupts = new TileInterrupts().asInput
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@ -192,6 +202,8 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
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val bp = Vec(nBreakpoints, new BP).asOutput
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val pmp = Vec(nPMPs, new PMP).asOutput
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val counters = Vec(nPerfCounters, new PerfCounterIO)
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val inst = Vec(retireWidth, UInt(width = iLen)).asInput
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val trace = Vec(retireWidth, new TracedInstruction).asOutput
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}
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class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Parameters) extends CoreModule()(p)
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@ -506,15 +518,14 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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assert(!io.singleStep || io.retire <= UInt(1))
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assert(!reg_singleStepped || io.retire === UInt(0))
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val epc = ~(~io.pc | (coreInstBytes-1))
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val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
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Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
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Causes.load_access, Causes.store_access, Causes.fetch_access,
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Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
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val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
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when (exception) {
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val epc = ~(~io.pc | (coreInstBytes-1))
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val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
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Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch,
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Causes.load_access, Causes.store_access, Causes.fetch_access,
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Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
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val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)
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when (trapToDebug) {
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when (!reg_debug) {
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reg_debug := true
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@ -756,6 +767,16 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
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}
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}
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for (((t, insn), i) <- (io.trace zip io.inst).zipWithIndex) {
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t.exception := io.retire >= i && exception
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t.valid := io.retire > i || t.exception
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t.insn := insn
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t.addr := io.pc
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t.priv := Cat(reg_debug, reg_mstatus.prv)
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t.cause := Cat(cause(xLen-1), cause(log2Ceil(xLen)-1, 0))
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t.tval := badaddr_value
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}
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def chooseInterrupt(masks: Seq[UInt]): (Bool, UInt) = {
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val nonstandard = supported_interrupts.getWidth-1 to 12 by -1
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// MEI, MSI, MTI, SEI, SSI, STI, UEI, USI, UTI
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@ -16,7 +16,6 @@ class Instruction(implicit val p: Parameters) extends ParameterizedBundle with H
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val rvc = Bool()
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val inst = new ExpandedInstruction
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val raw = UInt(width = 32)
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val cinst = UInt(width = 32)
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require(coreInstBits == (if (usingCompressed) 16 else 32))
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}
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@ -96,7 +95,6 @@ class IBuf(implicit p: Parameters) extends CoreModule {
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exp.io.in := curInst
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io.inst(i).bits.inst := exp.io.out
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io.inst(i).bits.raw := curInst
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io.inst(i).bits.cinst := Mux(exp.io.rvc, curInst & 0xFFFF, curInst)
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if (usingCompressed) {
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val replay = ic_replay(j) || (!exp.io.rvc && (btbHitMask(j) || ic_replay(j+1)))
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@ -136,7 +136,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val ex_reg_replay = Reg(Bool())
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val ex_reg_cinst = Reg(Bits())
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val ex_reg_raw_inst = Reg(UInt())
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val mem_reg_xcpt_interrupt = Reg(Bool())
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val mem_reg_valid = Reg(Bool())
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@ -153,7 +153,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val mem_reg_sfence = Reg(Bool())
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val mem_reg_pc = Reg(UInt())
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val mem_reg_inst = Reg(Bits())
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val mem_reg_cinst = Reg(Bits())
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val mem_reg_raw_inst = Reg(UInt())
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val mem_reg_wdata = Reg(Bits())
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val mem_reg_rs2 = Reg(Bits())
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val take_pc_mem = Wire(Bool())
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@ -167,7 +167,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val wb_reg_sfence = Reg(Bool())
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val wb_reg_pc = Reg(UInt())
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val wb_reg_inst = Reg(Bits())
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val wb_reg_cinst = Reg(Bits())
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val wb_reg_raw_inst = Reg(UInt())
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val wb_reg_wdata = Reg(Bits())
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val wb_reg_rs2 = Reg(Bits())
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val take_pc_wb = Wire(Bool())
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@ -178,7 +178,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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// decode stage
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val ibuf = Module(new IBuf)
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val id_expanded_inst = ibuf.io.inst.map(_.bits.inst)
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val id_nonexpanded_inst = ibuf.io.inst.map(_.bits.cinst)
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val id_raw_inst = ibuf.io.inst.map(_.bits.raw)
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val id_inst = id_expanded_inst.map(_.bits)
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ibuf.io.imem <> io.imem.resp
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ibuf.io.kill := take_pc
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@ -335,7 +335,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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}
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}
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when (id_illegal_insn) {
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val inst = Mux(ibuf.io.inst(0).bits.rvc, ibuf.io.inst(0).bits.raw(15, 0), ibuf.io.inst(0).bits.raw)
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val inst = Mux(ibuf.io.inst(0).bits.rvc, id_raw_inst(0)(15, 0), id_raw_inst(0))
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ex_reg_rs_bypass(0) := false
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ex_reg_rs_lsb(0) := inst(log2Ceil(bypass_sources.size)-1, 0)
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ex_reg_rs_msb(0) := inst >> log2Ceil(bypass_sources.size)
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@ -344,7 +344,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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when (!ctrl_killd || csr.io.interrupt || ibuf.io.inst(0).bits.replay) {
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ex_reg_cause := id_cause
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ex_reg_inst := id_inst(0)
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ex_reg_cinst := id_nonexpanded_inst(0)
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ex_reg_raw_inst := id_raw_inst(0)
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ex_reg_pc := ibuf.io.pc
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ex_reg_btb_resp := ibuf.io.btb_resp
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}
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@ -405,7 +405,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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mem_reg_cause := ex_cause
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mem_reg_inst := ex_reg_inst
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mem_reg_cinst := ex_reg_cinst
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mem_reg_raw_inst := ex_reg_raw_inst
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mem_reg_pc := ex_reg_pc
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mem_reg_wdata := alu.io.out
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@ -453,7 +453,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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}
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wb_reg_cause := mem_cause
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wb_reg_inst := mem_reg_inst
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wb_reg_cinst := mem_reg_cinst
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wb_reg_raw_inst := mem_reg_raw_inst
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wb_reg_pc := mem_reg_pc
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}
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@ -513,10 +513,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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when (rf_wen) { rf.write(rf_waddr, rf_wdata) }
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// hook up control/status regfile
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csr.io.decode.csr := ibuf.io.inst(0).bits.raw(31,20)
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csr.io.decode.csr := id_raw_inst(0)(31,20)
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csr.io.exception := wb_xcpt
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csr.io.cause := wb_cause
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csr.io.retire := wb_valid
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csr.io.inst(0) := Cat(Mux(wb_reg_rvc, 0.U, wb_reg_inst >> 16), wb_reg_raw_inst(15, 0))
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csr.io.interrupts := io.interrupts
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csr.io.hartid := io.hartid
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io.fpu.fcsr_rm := csr.io.fcsr_rm
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@ -530,6 +531,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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csr.io.rw.addr := wb_reg_inst(31,20)
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csr.io.rw.cmd := Mux(wb_reg_valid, wb_ctrl.csr, CSR.N)
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csr.io.rw.wdata := wb_reg_wdata
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io.trace := csr.io.trace
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val hazard_targets = Seq((id_ctrl.rxs1 && id_raddr1 =/= UInt(0), id_raddr1),
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(id_ctrl.rxs2 && id_raddr2 =/= UInt(0), id_raddr2),
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@ -664,28 +666,24 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) }
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if (enableCommitLog) {
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val pc = Wire(SInt(width=xLen))
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pc := wb_reg_pc.asSInt
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val inst = wb_reg_inst
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val cinst = wb_reg_cinst
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val rd = RegNext(RegNext(RegNext(id_waddr)))
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val t = csr.io.trace(0)
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val rd = wb_waddr
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val wfd = wb_ctrl.wfd
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val wxd = wb_ctrl.wxd
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val has_data = wb_wen && !wb_set_sboard
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val priv = csr.io.status.prv
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when (wb_valid) {
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when (t.valid) {
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when (wfd) {
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printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, cinst, rd, rd+UInt(32))
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printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd+UInt(32))
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}
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.elsewhen (wxd && rd =/= UInt(0) && has_data) {
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printf ("%d 0x%x (0x%x) x%d 0x%x\n", priv, pc, cinst, rd, rf_wdata)
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printf ("%d 0x%x (0x%x) x%d 0x%x\n", t.priv, t.addr, t.insn, rd, rf_wdata)
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}
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.elsewhen (wxd && rd =/= UInt(0) && !has_data) {
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printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", priv, pc, cinst, rd, rd)
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printf ("%d 0x%x (0x%x) x%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.addr, t.insn, rd, rd)
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}
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.otherwise {
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printf ("%d 0x%x (0x%x)\n", priv, pc, cinst)
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printf ("%d 0x%x (0x%x)\n", t.priv, t.addr, t.insn)
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}
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}
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@ -695,11 +693,11 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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}
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else {
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printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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io.hartid, csr.io.time(31,0), wb_valid, wb_reg_pc,
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io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).addr(vaddrBitsExtended-1, 0),
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Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
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wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
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wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),
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wb_reg_cinst, wb_reg_cinst)
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csr.io.trace(0).insn, csr.io.trace(0).insn)
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}
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val max_core_cycles = PlusArg("max-core-cycles",
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@ -21,6 +21,7 @@ trait TileParams {
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val dcache: Option[DCacheParams]
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val rocc: Seq[RoCCParams]
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val btb: Option[BTBParams]
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val trace: Boolean
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}
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trait HasTileParameters {
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@ -37,6 +38,7 @@ trait HasTileParameters {
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def xLen: Int = p(XLen)
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def xBytes: Int = xLen / 8
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def iLen: Int = 32
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def pgIdxBits: Int = 12
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def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
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def vaddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
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@ -92,6 +94,10 @@ trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
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val reset_vector = UInt(INPUT, resetVectorLen)
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}
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trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
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val trace = tileParams.trace.option(Vec(tileParams.core.retireWidth, new TracedInstruction).asOutput)
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}
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/** Base class for all Tiles that use TileLink */
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abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
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with HasTileParameters
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@ -102,6 +108,7 @@ abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends
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class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
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with HasTileLinkMasterPortBundle
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with HasExternallyDrivenTileConstants
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with CanHaveInstructionTracePort
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class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: () => B) extends BareTileModule(_outer, _io)
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with HasTileParameters
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@ -75,5 +75,6 @@ trait HasCoreIO extends HasTileParameters {
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val ptw = new DatapathPTWIO().flip
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val fpu = new FPUCoreIO().flip
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val rocc = new RoCCCoreIO().flip
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val trace = Vec(coreParams.retireWidth, new TracedInstruction).asOutput
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}
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}
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@ -19,6 +19,7 @@ case class RocketTileParams(
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btb: Option[BTBParams] = Some(BTBParams()),
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dataScratchpadBytes: Int = 0,
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boundaryBuffers: Boolean = false,
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trace: Boolean = false,
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name: Option[String] = Some("tile"),
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externalMasterBuffers: Int = 0,
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externalSlaveBuffers: Int = 0) extends TileParams {
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@ -139,6 +140,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
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val core = Module(p(BuildCore)(outer.p))
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decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
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core.io.hartid := io.hartid // Pass through the hartid
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io.trace.foreach { _ := core.io.trace }
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outer.frontend.module.io.cpu <> core.io.imem
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outer.frontend.module.io.reset_vector := io.reset_vector
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outer.frontend.module.io.hartid := io.hartid
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@ -196,7 +198,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
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}
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lazy val module = new LazyModuleImp(this) {
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val io = new CoreBundle with HasExternallyDrivenTileConstants {
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val io = new CoreBundle with HasExternallyDrivenTileConstants with CanHaveInstructionTracePort {
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val master = masterNode.bundleOut
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val slave = slaveNode.bundleIn
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val asyncInterrupts = asyncIntNode.bundleIn
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@ -206,6 +208,7 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:
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// signals that do not change based on crossing type:
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rocket.module.io.hartid := io.hartid
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rocket.module.io.reset_vector := io.reset_vector
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io.trace.foreach { _ := rocket.module.io.trace.get }
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}
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}
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