rocket: connect uncrossed output interrupts

2017-09-27 12:53:19 -07:00 · 2017-09-27 12:53:19 -07:00 · f48bf2ac2f
parent 1fda05970a
commit f48bf2ac2f
1 changed files with 2 additions and 0 deletions
--- a/src/main/scala/tile/RocketTile.scala
+++ b/src/main/scala/tile/RocketTile.scala
@ -213,6 +213,8 @@ abstract class RocketTileWrapper(rtp: RocketTileParams, hartid: Int)(implicit p:

  def outputInterruptXingLatency: Int

+  intOutputNode.foreach { _ := rocket.intOutputNode.get }
+
  lazy val module = new LazyModuleImp(this) {
    val io = new CoreBundle
        with HasExternallyDrivenTileConstants