riscv/rocket-chip
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  • 9f08c484bd tilelink2: ToAXI4 provide FIFO order semantics Wesley W. Terpstra 2017-04-25 17:55:06 -0700
  • 61a6f94196 axi4: get unit tests legal again Wesley W. Terpstra 2017-04-21 17:13:51 -0700
  • bf5cb396b9 rocketchip: relax mmio no-interleaving requirement Wesley W. Terpstra 2017-04-21 17:13:09 -0700
  • 24f577c156 axi4: Deinterleaver ensures R channel ID does not change till last Wesley W. Terpstra 2017-04-21 17:12:35 -0700
  • b4188ee625 axi4: ToTL supporting pipelined MMIO Wesley W. Terpstra 2017-04-21 12:30:41 -0700
  • ca2cb033cd rocketchip: fix uses of AXI4 Fragmenter Wesley W. Terpstra 2017-04-20 18:54:50 -0700
  • e100a943ea axi4: simplify Fragmenter by using user bits Wesley W. Terpstra 2017-04-20 15:20:20 -0700
  • 7a1d107c9e rocketchip: include an ErrorSlave by default Wesley W. Terpstra 2017-04-20 12:09:02 -0700
  • 641a4d577a tilelink2: Error device for returning errors on demand Wesley W. Terpstra 2017-04-20 11:49:07 -0700
  • a580b17ece axi4: IdIndexer => reduce number of needed ids Wesley W. Terpstra 2017-04-20 11:20:16 -0700
  • 06efc01d96 axi4: an adapter to remove user bits Wesley W. Terpstra 2017-04-20 17:32:49 -0700
  • f1217519f1 axi4: RegisterRouter; concurrent response illegal in AXI Wesley W. Terpstra 2017-04-21 16:59:59 -0700
  • 5163ccd11f axi4: RegisterRouter supports user bits Wesley W. Terpstra 2017-04-20 17:58:07 -0700
  • de6ea9b442 axi4: support user bits in SRAM Wesley W. Terpstra 2017-04-20 17:43:41 -0700
  • 396ecacda4 AXI4: add an optional user bundle field Wesley W. Terpstra 2017-03-17 17:06:04 -0700
  • d6e69066a5 Fix ITIM loads (#716) Andrew Waterman 2017-05-01 17:41:25 -0700
  • dd85d7e0a0 I$: Don't raise io.resp.valid if io.s1_kill was high previous cycle Andrew Waterman 2017-04-28 15:02:21 -0700
  • d67738204f Interrupts: Less Pessimistic Synchronization (#714) Megan Wachs 2017-04-28 14:49:24 -0700
  • 9b688ce7e2 Merge pull request #707 from ucb-bar/itim Andrew Waterman 2017-04-28 02:55:01 -0700
  • 7416f2a17e Unbreak groundtest Andrew Waterman 2017-04-28 02:10:33 -0700
  • 8fd5ecdff8 Set io.cpu.resp.bits.addr for MMIO loads without affecting QoR Andrew Waterman 2017-04-27 19:46:39 -0700
  • 7c70aa593e Minor stylistic and QoR improvements to PLIC Andrew Waterman 2017-04-27 19:35:20 -0700
  • 3d0ed80ef6 new parameters ResetVectorBits, MaxHartIdBits, and MaxPriorityLevels Henry Cook 2017-04-27 15:22:52 -0700
  • bdb526a9f0 coreplex: DefaultCoreplex => RocketPlex Henry Cook 2017-04-27 14:51:28 -0700
  • 99de42d34c Swap order of ITIM WidthWidget and Fragmenter Andrew Waterman 2017-04-27 15:30:02 -0700
  • 8c10caeef9 Express PMP mask generation with incrementer, not adder Andrew Waterman 2017-04-27 14:31:50 -0700
  • e99fa057ac cleanup scratchpad nodes Henry Cook 2017-04-27 14:02:05 -0700
  • b2b4725522 Fix zero-width wire issues when ITIM is disabled Andrew Waterman 2017-04-26 22:43:00 -0700
  • e23ee274f6 Size hartid field with NTiles, not XLen Andrew Waterman 2017-04-26 20:11:43 -0700
  • dc753bfa95 Fix I$ elaboration when ITIM is disabled Andrew Waterman 2017-04-26 18:24:39 -0700
  • 80d826b94a Make DTIM deduplicatable Andrew Waterman 2017-04-26 15:54:43 -0700
  • 418879a47f Add Instruction Tightly Integrated Memory Andrew Waterman 2017-04-24 17:14:23 -0700
  • ee6702e5e0 Support indexing 1-entry Seqs Andrew Waterman 2017-04-26 12:19:21 -0700
  • 2e23d46631 Use val instead of def in ECC calculations Andrew Waterman 2017-04-25 20:18:13 -0700
  • 635f119422 Merge pull request #709 from ucb-bar/bump-hardfloat Henry Cook 2017-04-26 16:47:49 -0700
  • ebe27614d2 bump hardfloat Henry Cook 2017-04-26 15:37:29 -0700
  • 0a9f632cb0 Merge pull request #708 from ucb-bar/debug_busy_data Henry Cook 2017-04-26 14:32:10 -0700
  • 7ad4cc36f7 debug: Prevent writes to DATA/PROGBUF when busy Megan Wachs 2017-04-26 11:11:21 -0700
  • e9db531e81 point to riscv-tools README for dependencies (#705) Megan Wachs 2017-04-25 20:20:27 -0700
  • 1bdb247002 Merge pull request #697 from ucb-bar/async_queue_option Henry Cook 2017-04-25 17:43:28 -0700
  • 7f5f1c7631 Merge branch 'master' into async_queue_option Henry Cook 2017-04-25 14:58:11 -0700
  • 95591cc608 Merge pull request #704 from ucb-bar/verbose-require Henry Cook 2017-04-25 14:57:58 -0700
  • 9bb0d92381 Merge branch 'master' into async_queue_option Henry Cook 2017-04-25 11:23:22 -0700
  • 60d71efa36 ahb: make hreadyout fuzzing a sram parameter Henry Cook 2017-04-25 11:10:19 -0700
  • ca435c2f40 uncore: more verbose requires Henry Cook 2017-04-25 11:09:09 -0700
  • f3ab23d068 dcache: fix stupidly wrong crossing comparison (#703) Wesley W. Terpstra 2017-04-25 09:18:41 -0700
  • 4807ce7ced dcache: put a flow Q to absorb back-pressure without restarting pipeline (#701) Wesley W. Terpstra 2017-04-24 23:28:04 -0700
  • 9c1d126965 Allow speculative fetch to uncacheable memory if it hits in I$ (#700) Wesley W. Terpstra 2017-04-24 19:12:37 -0700
  • 11ff4dfbb9 rocket: seip (int 9) is only present if VM is enabled (#699) Wesley W. Terpstra 2017-04-24 15:58:33 -0700
  • d0f3004097 tilelink2: help tools save some registers in the WidthWidget (#691) Wesley W. Terpstra 2017-04-24 15:13:58 -0700
  • 65928dc6a0 Don't push RAS for "auipc ra, X; jalr ra, ra, Y" Andrew Waterman 2017-04-24 01:16:21 -0700
  • 36a7971975 Bypass scoreboard to reduce MMIO latency Andrew Waterman 2017-04-22 22:13:40 -0700
  • 845e6f7458 Filter out duplicate test suites Andrew Waterman 2017-04-22 22:12:26 -0700
  • f2d4cb8152 Update RAS speculatively from fetch stage Andrew Waterman 2017-04-22 21:35:19 -0700
  • 3b2c15b648 Use tininess-after-rounding in FPU Andrew Waterman 2017-04-21 18:01:56 -0700
  • c36c171202 Use correct interrupt priority order Andrew Waterman 2017-04-21 18:01:32 -0700
  • bf861293d9 Add ShiftQueue; use it Andrew Waterman 2017-04-21 18:01:09 -0700
  • d24d8ff84b Don't stall the frontend, making it easier to add more features later Andrew Waterman 2017-04-19 16:51:39 -0700
  • 061a0adceb Fetch smaller parcels from the I$ Andrew Waterman 2017-04-18 17:55:04 -0700
  • 0aa8f7d61d Add narrowData option to AsyncQueue. Ben Keller 2017-04-21 16:31:17 -0700
  • c72b15f2a0 Down with any require() statement that makes me RTFC Megan Wachs 2017-04-21 14:49:48 -0700
  • 458d80cb18 For Verilator, rename +start to +dump-start to match VCS Andrew Waterman 2017-03-31 11:38:29 -0700
  • 2faf8ea239 Add +dump-start=N option to VCS Andrew Waterman 2017-03-31 11:37:37 -0700
  • 54820e094d Make more require statements in diplomacy verbose (#693) Henry Cook 2017-04-20 13:18:39 -0700
  • ef8a819763 Miscellaneous periphery improvements (#689) Henry Cook 2017-04-20 11:28:00 -0700
  • 9002e7e532 debug: Debug Module needs to handle DMI NOPs even if DTM won't send them. Megan Wachs 2017-04-20 09:18:39 -0700
  • cc7f0a5b7a debug: whitespace cleanup Megan Wachs 2017-04-19 14:07:21 -0700
  • 5934779082 debug: Clean up ValidReg assertion. Megan Wachs 2017-04-19 13:56:47 -0700
  • 0c013a56c0 debug: Make DMI NOPs really NOPs. Megan Wachs 2017-04-19 13:17:22 -0700
  • 67404a665b When not using a cache, LR/SC isn't legal even on cacheable memory Andrew Waterman 2017-04-19 16:52:23 -0700
  • 1be13d6b4c PLIC: To avoid hazard between enable -> claim, enforce concurrency=1 Megan Wachs 2017-04-19 19:44:51 -0700
  • 3dfd584075 regmapper: remove the Pipe in the RegMapper Queue Megan Wachs 2017-04-19 18:57:23 -0700
  • b4d17c76d1 coreplex: make rational+synchronous crossing configurable (#688) Wesley W. Terpstra 2017-04-19 16:16:05 -0700
  • 408107447c debug: DMI response should be busy, not zero, when there is an error. (#685) Megan Wachs 2017-04-18 21:41:52 -0700
  • d82a0dc231 Mitigate D$ exception critical path, yet again Andrew Waterman 2017-04-17 23:48:30 -0700
  • c99ce7ce5d Only report D$ exceptions on not-nacked accesses Andrew Waterman 2017-04-17 22:42:16 -0700
  • 5934c7b4b9 Fix description of LR/SC test suites Andrew Waterman 2017-04-17 21:31:06 -0700
  • a956b78dd2 In TLBPermissions, merge across some region types Andrew Waterman 2017-04-17 20:44:29 -0700
  • 6de6f38894 Pipeline D$ exception response into s2 Andrew Waterman 2017-04-14 23:57:32 -0700
  • 657f4d4e0c Permit early grant acks to broadcast hub Andrew Waterman 2017-04-17 17:27:00 -0700
  • cc9ec1d51a Send D$ grant acks early; accept release acks early Andrew Waterman 2017-04-17 17:25:29 -0700
  • 728569c717 Reduce access-exception generation critical path Andrew Waterman 2017-04-15 00:53:31 -0700
  • a59a3f15e4 Disable LR/SC tests for scratchpad configs Andrew Waterman 2017-04-14 18:23:44 -0700
  • c366007a0d Tighten PMAs for LR/SC and misaligned accesses Andrew Waterman 2017-04-14 18:22:12 -0700
  • 74a7838de0 In TLBPermissions, don't merge regions of different types Andrew Waterman 2017-04-14 16:18:11 -0700
  • 7871ec82c4 Guarantee probe forward progress during LR storm Andrew Waterman 2017-04-14 01:09:13 -0700
  • 71eaed7d60 Merge pull request #675 from ucb-bar/debug_no_preexec Yunsup Lee 2017-04-18 03:10:27 +0900
  • 1ad5ef7aa2 bump chisel Yunsup Lee 2017-04-17 00:24:09 -0700
  • debcbca7de Make PMP tolerant to PA size << VA size Andrew Waterman 2017-04-15 00:54:49 -0700
  • aad4f350bf bump tools Yunsup Lee 2017-04-14 23:42:57 -0700
  • a454edaaf7 Treat exceptions as steps for the purposes of single-stepping Andrew Waterman 2017-04-14 15:12:17 -0700
  • 9cf86fa105 debug: checkpoint pointing to riscv-tools that picks up some tweaks in the debug riscv-tests Megan Wachs 2017-04-14 10:33:05 -0700
  • 9a6e7afc93 debug: bump OpenOCD to latest version of newprogram (with Examined RISC-V core message) Megan Wachs 2017-04-14 10:32:06 -0700
  • af6b2d8051 debug: DATA Region has to be aligned for ld/sd to correctly detect 64-bit cores. Megan Wachs 2017-04-13 12:27:32 -0700
  • b44d5f9386 debug: correctly consider .transfer bit in COMMAND Megan Wachs 2017-04-12 21:18:01 -0700
  • 79477fbea6 debug: Properly consider 'transfer' bit Megan Wachs 2017-04-11 15:50:32 -0700
  • 2dc4be6294 debug: remove preexec. Simplify the state machine since you can always just 'execute' once. Megan Wachs 2017-04-11 09:27:02 -0700
  • c5cb8b714f debug: Bump version and location of OpenOCD to pick up fix for off-by-1 in hartsel Megan Wachs 2017-04-11 09:26:33 -0700
  • db5d0737f0 Merge pull request #682 from ucb-bar/jchang Wesley W. Terpstra 2017-04-14 19:35:17 -0700
  • 7b8af96fc2 diplomacy: use circles for nodes again Wesley W. Terpstra 2017-04-14 17:01:12 -0700