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@ -52,19 +52,24 @@ object DsbRegAddrs{
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def RESUMING = 0x108
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def EXCEPTION = 0x10C
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def FLAGS = 0x400
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def ROMBASE = 0x800
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def RESUME = 0x804
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def WHERETO = 0x300
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def ABSTRACT = 0x340 - 8
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def PROGBUF = 0x340
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// This needs to be aligned for up to lq/sq
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// This shows up in HartInfo
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// This shows up in HartInfo, and needs to be aligned
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// to enable up to LQ/SQ instructions.
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def DATA = 0x380
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//Not implemented: Serial.
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// We want DATA to immediately follow PROGBUF so that we can
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// use them interchangeably.
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def PROGBUF(cfg:DebugModuleConfig) = {DATA - (cfg.nProgramBufferWords * 4)}
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// We want abstract to be immediately before PROGBUF
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// because we auto-generate 2 instructions.
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def ABSTRACT(cfg:DebugModuleConfig) = PROGBUF(cfg) - 8
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def FLAGS = 0x400
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def ROMBASE = 0x800
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}
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@ -226,8 +231,8 @@ class DebugCtrlBundle (nComponents: Int)(implicit val p: Parameters) extends Par
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* provide the default MTVEC since it is mapped
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* to address 0x0.
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*
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* DebugModule is responsible for control registers and RAM. The Debug ROM is in a
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* seperate module. It runs partially off of the dmiClk (e.g. TCK) and
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* DebugModule is responsible for control registers and RAM, and
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* Debug ROM. It runs partially off of the dmiClk (e.g. TCK) and
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* the TL clock. Therefore, it is divided into "Outer" portion (running
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* of off dmiClock and dmiReset) and "Inner" (running off tlClock and tlReset).
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* This allows DMCONTROL.haltreq, hartsel, dmactive, and ndreset to be
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@ -354,8 +359,7 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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io.debugInterrupts(component)(0) := debugIntRegs(component)
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}
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// Halt request registers are written by write to DMCONTROL.haltreq
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// and cleared by writes to DMCONTROL.resumereq.
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// Halt request registers are set & cleared by writes to DMCONTROL.haltreq
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// resumereq also causes the core to execute a 'dret',
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// so resumereq is passed through to Inner.
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// hartsel must also be used by the DebugModule state machine,
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@ -367,11 +371,8 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod
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when (~dmactive) {
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debugIntNxt(component) := false.B
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}. otherwise {
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when (DMCONTROLWrEn) {
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when (DMCONTROLWrData.hartsel === component.U) {
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debugIntNxt(component) := (debugIntRegs(component) | DMCONTROLWrData.haltreq) &
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~(DMCONTROLWrData.resumereq)
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}
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when (DMCONTROLWrEn && DMCONTROLWrData.hartsel === component.U) {
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debugIntNxt(component) := DMCONTROLWrData.haltreq
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}
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}
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}
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@ -597,8 +598,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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}.elsewhen (errorHaltResume) {
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ABSTRACTCSReg.cmderr := DebugAbstractCommandError.ErrHaltResume.id.U
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}.otherwise {
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//TODO: Should be write-1-to-clear & ~ABSTRACTCSWrData.cmderr
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when (ABSTRACTCSWrEn /* && ABSTRACTCSWrData.cmderr === 0.U*/){
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when (ABSTRACTCSWrEn){
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ABSTRACTCSReg.cmderr := ABSTRACTCSReg.cmderr & ~(ABSTRACTCSWrData.cmderr);
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}
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}
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@ -741,35 +741,15 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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// "Variable" ROM Generation
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//--------------------------------------------------------------
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val goProgramBuffer = Wire(init = false.B)
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val goAbstract = Wire(init = false.B)
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val whereToReg = Reg(UInt(32.W))
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val jalProgBuf = Wire(init = (new GeneratedUJ()).fromBits(rocket.Instructions.JAL.value.U))
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jalProgBuf.setImm(PROGBUF - WHERETO)
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jalProgBuf.rd := 0.U
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val goReg = Reg(Bool())
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val goAbstract = Wire(init = false.B)
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val jalAbstract = Wire(init = (new GeneratedUJ()).fromBits(rocket.Instructions.JAL.value.U))
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jalAbstract.setImm(ABSTRACT - WHERETO)
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jalProgBuf.rd := 0.U
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when (~io.dmactive) {
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whereToReg := 0.U
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}.otherwise{
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when (goProgramBuffer) {
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whereToReg := jalProgBuf.asUInt()
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}.elsewhen (goAbstract) {
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whereToReg := jalAbstract.asUInt()
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}
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}
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val goReg = Reg(Bool())
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jalAbstract.setImm(ABSTRACT(cfg) - WHERETO)
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when (~io.dmactive){
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goReg := false.B
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}.otherwise {
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when (goProgramBuffer | goAbstract) {
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when (goAbstract) {
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goReg := true.B
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}.elsewhen (hartGoingWrEn){
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assert(hartGoingId === 0.U, "Unexpected 'GOING' hart.")//Chisel3 #540 %x, expected %x", hartGoingId, 0.U)
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@ -864,7 +844,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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nop.imm := 0.U
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when (goAbstract) {
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abstractGeneratedMem(0) := Mux(/*TODO: accessRegisterCommandReg.transfer*/true.B,
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abstractGeneratedMem(0) := Mux(accessRegisterCommandReg.transfer,
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Mux(accessRegisterCommandReg.write,
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// To write a register, we need to do LW.
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abstractGeneratedI.asUInt(),
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@ -872,7 +852,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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abstractGeneratedS.asUInt()),
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nop.asUInt()
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)
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abstractGeneratedMem(1) := Mux(/*TODO accessRegisterCommandReg.postexec*/ false.B,
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abstractGeneratedMem(1) := Mux(accessRegisterCommandReg.postexec,
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nop.asUInt(),
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rocket.Instructions.EBREAK.value.U)
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}
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@ -888,14 +868,15 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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RESUMING -> Seq(WNotify(sbIdWidth, hartResumingId, hartResumingWrEn)),
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EXCEPTION -> Seq(WNotify(sbIdWidth, hartExceptionId, hartExceptionWrEn)),
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DATA -> abstractDataMem.map(x => RegField(8, x)),
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PROGBUF -> programBufferMem.map(x => RegField(8, x)),
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PROGBUF(cfg)-> programBufferMem.map(x => RegField(8, x)),
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// These sections are read-only.
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ROMBASE -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W))),
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FLAGS -> flags.map{x => RegField.r(8, x.asUInt())},
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WHERETO -> Seq(RegField.r(32, whereToReg)),
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ABSTRACT -> abstractGeneratedMem.map(x => RegField.r(32, x))
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)
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WHERETO -> Seq(RegField.r(32, jalAbstract.asUInt)),
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ABSTRACT(cfg)-> abstractGeneratedMem.map{x => RegField.r(32, x)},
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FLAGS -> flags.map{x => RegField.r(8, x.asUInt())},
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ROMBASE -> DebugRomContents().map(x => RegField.r(8, (x & 0xFF).U(8.W)))
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)
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// Override System Bus accesses with dmactive reset.
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when (~io.dmactive){
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@ -909,7 +890,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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object CtrlState extends scala.Enumeration {
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type CtrlState = Value
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val Waiting, CheckGenerate, PreExec, Abstract, PostExec = Value
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val Waiting, CheckGenerate, Exec = Value
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def apply( t : Value) : UInt = {
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t.id.U(log2Up(values.size).W)
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@ -945,7 +926,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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val commandRegIsUnsupported = Wire(init = true.B)
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val commandRegBadHaltResume = Wire(init = false.B)
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when (commandRegIsAccessRegister) {
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when ((accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
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when (!accessRegisterCommandReg.transfer || (accessRegisterCommandReg.regno >= 0x1000.U && accessRegisterCommandReg.regno <= 0x101F.U)){
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commandRegIsUnsupported := false.B
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commandRegBadHaltResume := ~hartHalted
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}
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@ -957,13 +938,12 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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//------------------------
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// Variable ROM STATE MACHINE
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// -----------------------
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when (ctrlStateReg === CtrlState(Waiting)){
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when (wrAccessRegisterCommand || regAccessRegisterCommand) {
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ctrlStateNxt := CtrlState(CheckGenerate)
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}
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}.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){
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// We use this state to ensure that the COMMAND has been
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@ -977,47 +957,11 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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errorHaltResume := true.B
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ctrlStateNxt := CtrlState(Waiting)
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}.otherwise {
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when (accessRegisterCommandReg.preexec) {
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ctrlStateNxt := CtrlState(PreExec)
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goProgramBuffer := true.B
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}.otherwise {
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ctrlStateNxt := CtrlState(Abstract)
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goAbstract := true.B
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}
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}
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}.elsewhen (ctrlStateReg === CtrlState(PreExec)) {
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// We can't just look at 'hartHalted' here, because
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// hartHaltedWrEn is overloaded to mean 'got an ebreak'
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// which may have happened when we were already halted.
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when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
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ctrlStateNxt := CtrlState(Abstract)
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ctrlStateNxt := CtrlState(Exec)
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goAbstract := true.B
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}
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when(hartExceptionWrEn) {
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assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")// Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
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ctrlStateNxt := CtrlState(Waiting)
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errorException := true.B
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}
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}.elsewhen (ctrlStateReg === CtrlState(Abstract)) {
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// We can't just look at 'hartHalted' here, because
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// hartHaltedWrEn is overloaded to mean 'got an ebreak'
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// which may have happened when we were already halted.
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when(goReg === false.B && hartHaltedWrEn && (cfg.hartIdToHartSel(hartHaltedId) === selectedHartReg)){
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when (accessRegisterCommandReg.postexec) {
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ctrlStateNxt := CtrlState(PostExec)
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goProgramBuffer := true.B
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}.otherwise {
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ctrlStateNxt := CtrlState(Waiting)
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}
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}
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when(hartExceptionWrEn) {
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assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540 %x, expected %x", hartExceptionId, selectedHartReg)
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ctrlStateNxt := CtrlState(Waiting)
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errorUnsupported := true.B
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}
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}.elsewhen (ctrlStateReg === CtrlState(PostExec)) {
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}.elsewhen (ctrlStateReg === CtrlState(Exec)) {
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// We can't just look at 'hartHalted' here, because
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// hartHaltedWrEn is overloaded to mean 'got an ebreak'
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@ -1027,7 +971,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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}
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when(hartExceptionWrEn) {
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assert(hartExceptionId === 0.U, "Unexpected 'EXCEPTION' hart")//Chisel3 #540, %x, expected %x", hartExceptionId, 0.U)
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ctrlStateNxt := CtrlState(Waiting)
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ctrlStateNxt := CtrlState(Waiting)
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errorException := true.B
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}
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}
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@ -1040,6 +984,7 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p:
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}
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}
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// Wrapper around TL Debug Module Inner and an Async DMI Sink interface.
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// Handles the synchronization of dmactive, which is used as a synchronous reset
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// inside the Inner block.
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