Colin Schmidt
97d0e195ae
Merge pull request #28 from ucb-bar/yusnup
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Don't re-generate the .d files on "make clean"
2015-11-12 00:46:21 -08:00
Palmer Dabbelt
07f0e6be94
Don't re-generate the .d files on "make clean"
2015-11-12 00:41:55 -08:00
Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74
actually use backendBuffering in front of unwrapper/converter chain
2015-11-09 11:50:18 -08:00
Yunsup Lee
1e772daeea
no spaces in Makefrag
2015-11-05 16:42:05 -08:00
Howard Mao
cb0c2df051
update fpga-zynq
2015-11-05 10:50:13 -08:00
Howard Mao
42e7067400
bump uncore
2015-11-05 10:49:25 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Howard Mao
fb501e75c0
fixes for sub-block TL requests in uncore
2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
Howard Mao
ba5a6af05c
correctly stripe data across memory channels in simulation
2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Colin Schmidt
032bdd0601
Merge pull request #24 from ucb-bar/regression-master
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Add a "--master" flag to the regression script
2015-10-29 14:15:44 -07:00
Palmer Dabbelt
3d2a4ffdd6
Add a "--master" flag to the regression script
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I want to be able to test the master of riscv-gnu-toolchain against the current
RTL as part of the buildbot. This flag takes a list of repositories (by their
submodule path) and updates those to the current master, which facilitates that
check.
2015-10-29 14:11:26 -07:00
Howard Mao
eb62ff6a50
add queues between Nasti -> TL converter and Nasti interconnect
2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
Howard Mao
c3a7dcf0ab
fix missing cde library dependencies in submodules
2015-10-23 15:05:19 -07:00
Colin Schmidt
854feab08e
add knob and constraint dumping
2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Henry Cook
47bc193c16
added CDE library as submodule
2015-10-21 18:24:16 -07:00
Howard Mao
21f342ad42
fix typo causing L2 cache configuration to fail
2015-10-21 13:37:33 -07:00
Howard Mao
d5a75fd113
accidentally committed some code I didn't mean to in Rocket
2015-10-21 09:21:54 -07:00
Howard Mao
693a4ae00e
fix some more memory system bugs
2015-10-20 23:29:59 -07:00
Howard Mao
c311c9938e
nitpicky declaration move
2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
Howard Mao
4346111d2a
fix remaining vsim harness typo
2015-10-19 20:20:14 -07:00
Howard Mao
896aa892d1
bump uncore for TL -> NASTI converter fix
2015-10-19 15:31:59 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2
make sure TL parameters change properly throughout
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* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75
added HasAddrMapParameters and GlobalAddrMap
2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1
inject params at top-level for MemDessert
2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57
Removed all traces of params
2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3
refactor MemIO to not use params
2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907
refactor NASTI to not use param; new AddrMap class
2015-10-06 11:41:47 -07:00
Andrew Waterman
c2ad0b7dd4
Unfuck fpga-zynq submodule pointer
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Sorry, Scott.
2015-10-01 15:00:35 -07:00
