f8a0829134
rocketchip: remove clint; it moves into coreplex
2016-10-31 11:42:13 -07:00
5090ff945b
DebugModule: Be more paranoid about addressing corner cases.
2016-10-31 11:42:13 -07:00
b99662796d
PLIC: converted to TL2
2016-10-31 11:42:13 -07:00
bddfa4d69b
Debug: make address configurable
2016-10-31 11:42:13 -07:00
c3dacca39a
rocketchip: remove pbus; TL2 has swallowed it completely
2016-10-31 11:42:08 -07:00
10d084b9f3
DebugModule: Use the power of RegisterRouter to simplify the DebugROM code.
2016-10-31 11:41:18 -07:00
3df797fcab
rocketchip: replace TL1 MMIO with an example of TL2 MMIO
2016-10-31 11:41:18 -07:00
650f6fb23f
diplomacy: add BlindNodes for use as external ports
2016-10-31 11:41:18 -07:00
0edcd3304a
diplomacy Nodes: leave flipping to the MixedNode implementation
2016-10-31 11:41:18 -07:00
082f338432
diplomacy Nodes: remove useless indirection
2016-10-31 11:41:18 -07:00
ec2d23b8b7
rocketchip: Bundle-slices need access to the outer LazyModule
...
We need this change in order for some ports to use parameters that result
from LazyModule diplomacy.
Now you can eat your cake too!
2016-10-31 11:41:18 -07:00
0ae45d0f24
rocketchip: bundle (=> B) need not be delayed; Module is constructed later
2016-10-31 11:41:18 -07:00
0dbda2f07d
rocketchip: remove obsolete pDevices used during TL1=>2 migration
2016-10-31 11:41:18 -07:00
af924d8c51
DebugModule: Instantiate TL2 DebugModule in BaseCoreplex
2016-10-31 11:41:18 -07:00
d530ef7236
DebugModule: translate to TL2 with {32,64}-bit XLen width
2016-10-31 11:41:18 -07:00
f0e9a2a081
Fix PutBlock after Release bug
...
There is logic in the broadcast hub to skip the outer acquire if there
is an outgoing release, since the data will be written out through the
release channel. However, this will cause an issue in the case of
PutBlock requests. If the tail beats of the PutBlock show up after the
outer release has already been sent, the data will be corrupted.
The fix is to make the outer release block if there are pending
inner PutBlock beats.
2016-10-28 18:26:34 -07:00
cb81ea516c
add regression test for put-after-release bug
2016-10-28 18:26:34 -07:00
fa8844d5c3
properly use rocket MT_ constants in regression tests
2016-10-28 18:26:34 -07:00
e45b41b4b6
Don't rely on SeqMem output after read-enable is low
2016-10-27 23:44:10 -07:00
900a7bbcf1
add PutAtomic support to width adapter
2016-10-26 09:58:26 -07:00
fc5eb7cc64
Fixed AsyncFifo with reset messaging
2016-10-25 16:45:08 -07:00
fd2d48acda
lazy_module: If the user actually specifies a name, just use it without appending module name.
2016-10-25 15:58:09 -07:00
a807c922d0
diplomacy: take names from the outermost common node
2016-10-25 15:58:09 -07:00
fee67c4abf
diplomacy: add methods to find {out,in}ner-most common node
2016-10-25 15:58:09 -07:00
67ab27f5a5
diplomacy: guess the LazyModule name from the containing class
2016-10-25 15:58:09 -07:00
4d50733548
tilelink2 ToAXI4: use helper method for a_last ( #418 )
2016-10-25 10:16:42 -07:00
7dc97674d6
rocketchip: include an socBus between l1tol2 and periphery ( #415 )
...
Sometimes we have high performance devices that go inbetween.
2016-10-24 23:56:09 -07:00
a5ac106bb8
axi4 ToTL: fix decode error arbitration ( #417 )
...
When selecting between error generation on R and real data on R,
correctly calculate the R backpressure.
This bug manifests when a valid request is immediately followed by
an invalid request, wedging the R channel.
2016-10-24 22:15:19 -07:00
4c815f7958
tilelink2 Parameters: fix {contains,supports}Safe ( #416 )
...
When there is only one manager, you still want to know if the address
was wrong on the link to that manager!
2016-10-24 20:37:04 -07:00
8bfd6bcd4d
axi4: ensure we accept AR before reporting R ( #411 )
2016-10-21 21:02:05 -07:00
85f3788ab5
initialize s2_hit to solve #401
2016-10-21 14:53:55 -07:00
7c334e3c34
axi4 ToTL: shorter critical path on Q.bits if errors go first
2016-10-17 01:00:49 -07:00
73010c79a3
axi4 ToTL: handle bad AXI addresses
2016-10-17 00:12:26 -07:00
501d6d689f
axi4: Test ToTL
2016-10-16 22:04:06 -07:00
5a1da63b5a
axi4: prototype ToTL adapter
2016-10-16 22:04:01 -07:00
72e5a97d40
tilelink2: factor out the OH1ToOH function
2016-10-16 22:04:01 -07:00
d09f43c32f
axi4 Bundles: add a size calculation helper
...
The old version was wrong.
Inverting before the << has a different width.
This means you end up with high bits set.
2016-10-16 22:04:01 -07:00
20288729b9
tilelink2 Isolation: cross the valid signals as well
...
Refactor the code to be less copy-pasty
2016-10-14 18:28:36 -07:00
680a944f07
regmapper RegisterCrossing: safe AsyncQueues are overkill here
2016-10-14 18:28:31 -07:00
ac0bb841da
AsyncQueue: cope with far reset propagation delay
2016-10-14 18:05:35 -07:00
8f3c2ddfc3
tilelink2 Crossing: these asserts should be done by the AsyncQueue
2016-10-14 16:54:09 -07:00
a82cfb8306
tilelink2: replace addr_hi with address ( #397 )
...
When faced with ambiguous routing of wmask=0, we decided to include
all the address bits. Hopefully in most cases the low bits will be
optimized away anyway.
2016-10-14 14:09:39 -07:00
4e40f9bb59
tilelink2 Nodes: appease the PC police
2016-10-13 17:02:18 -07:00
54b73aef57
tilelink2: WidthWidget and Fragmenter no longer erase latency
2016-10-13 17:02:18 -07:00
200cf3dd13
tilelink2 Nodes: include some options to test for conformance
2016-10-13 17:02:18 -07:00
5d5b5a66f4
tilelink2 RAMModel: fix a write-bad-data bug
2016-10-13 17:02:17 -07:00
e5a1483358
tilelink2 Fragmenter: eliminate most of the registers on A
2016-10-13 17:02:17 -07:00
99c7003d11
tilelink2: allow preemption of Fragmenter and WidthWidget
2016-10-13 17:02:17 -07:00
b42cfdc9dd
tilelink2 Arbiter: there is only one winner
2016-10-13 17:02:17 -07:00
b6e9b0c558
tilelink2 Arbiter: allow preemption of first beat
2016-10-13 17:02:17 -07:00