Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.
* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
(1) Introduce tracegen.py, a script that invokes the emulator (built
with TraceGenConfig), sending a SIGTERM once all cores are finished.
(2) Update toaxe.py to gather some statistics about the trace.
(3) Introduce tracestats.py, which displays the stats in a useful way.
(4) Introduce tracegen+check.py, a top-level script that generates
traces, checks them, and emits stats. If this commit is pulled, it
should be done after pulling my latest groundtest commit.
