35a983275e
Guarantee one-hotness of BTB entries
2016-07-06 15:58:01 -07:00
bbf780725f
add NastiReadIO and NastiWriteIO bundles
2016-07-06 15:13:04 -07:00
b10d306b4a
add option to log L2 cache transactions for easier debugging
2016-07-06 14:59:09 -07:00
64afc795fd
make sure voluntary releases don't get allocated to L2WritebackUnit
2016-07-06 14:10:45 -07:00
2a146155fc
Update to new priv-1.9 PTE format
2016-07-06 10:15:59 -07:00
8625f9ea0c
Update PTE format
2016-07-06 03:20:41 -07:00
c0e6ecebfc
Fix BTB perf bug
...
In rare cases, it would replace into a different row than it recorded.
2016-07-06 03:16:05 -07:00
f3e22984d5
Remove uarch counters
...
These will be replaced with the indirect TDR scheme used by breakpoints.
2016-07-06 01:41:41 -07:00
25fdabdd59
Don't implicitly create Vecs, since they're heavyweight
2016-07-06 01:41:31 -07:00
8bd7e3932b
Implement priv-1.9 PTE scheme
2016-07-05 19:19:49 -07:00
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
b105076996
fix ID mapper to disallow two in-flight requests with the same inner ID
2016-07-05 17:41:46 -07:00
af76837970
conform to new NastiWriteDataChannel interface
2016-07-05 17:41:46 -07:00
ee624b1c6e
make NastiSmallTest a bit more intensive
2016-07-05 17:31:51 -07:00
96f09003f2
use options for NastiWriteDataChannel write mask
2016-07-05 16:03:25 -07:00
4c07aedfad
Rewrite BRAMSlave to infer a single BRAM instance
2016-07-05 14:21:21 -07:00
8c5fd86f9b
fix tracegen module and scripts
2016-07-05 13:50:17 -07:00
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
702444709a
make sure pending bits updated for all releases
2016-07-05 12:08:22 -07:00
06ed9c5794
add a single-entry queue in front of acquire and release for bufferless broadcast hub
2016-07-05 12:08:22 -07:00
67bac383e3
hopefully fixed last bugs in Bufferless
2016-07-05 12:08:22 -07:00
a35388bc27
fix merging of same xact ID puts/gets
2016-07-05 12:08:22 -07:00
51f7bf1511
fix Bufferless voluntary release issue
2016-07-05 12:08:22 -07:00
afc51c4a35
make sure TL -> NASTI converter handles multibeat transactions properly
2016-07-05 12:08:22 -07:00
ebefe57036
simplify BTB fetchWidth=1 special case
2016-07-04 23:43:47 -07:00
61a44dcfc3
add regression test for L1 voluntary releases
2016-07-04 17:02:24 -07:00
85808f8cbb
Clean up PseudoLRU code
2016-07-02 15:09:12 -07:00
2d325df60c
Improve PTW simulation performance
2016-07-02 14:34:18 -07:00
5aa8ef1855
Remove invalidation support from BTB
...
Validating the target PC in the pipeline is cheaper than maintaining
the valid bits and control logic to guarantee the BTB won't ever
mispredict branch targets.
2016-07-02 14:27:29 -07:00
663002ec0c
Improve TLB simulation performance
2016-07-02 14:26:05 -07:00
af51b6f363
bump groundtest and uncore
2016-07-01 18:13:46 -07:00
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
7f0a583515
timeout for Nasti tests
2016-07-01 18:11:44 -07:00
caa9ca24b9
NASTI -> TL converter also uses ID mapper
2016-07-01 18:11:29 -07:00
37599fb0c9
fix use of width adapter in NastiConverterTest
2016-07-01 17:05:41 -07:00
39bee5198d
Nasti Puts: decode wmask to determine addr_byte() and op_size()
...
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
2016-07-01 16:49:32 -07:00
e163a23583
fix another bug in Widener
2016-07-01 16:24:48 -07:00
10a46a36ae
fix full_addr() function in TileLink
2016-07-01 15:17:41 -07:00
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
61e3e5b45a
more WIP on fixing Bufferless
2016-06-30 18:29:51 -07:00
0eedffa82f
WIP: Fix BufferlessBroadcastHub
2016-06-30 18:29:51 -07:00
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
ce46f523c9
make sure Widener uses proper parameters to generate acquire/grant
2016-06-30 18:17:16 -07:00
f46efb671d
add multi-transaction timer and add to Comparator
2016-06-30 17:39:10 -07:00
a0b1772404
change TileLinkWidthAdapter interface
2016-06-30 15:50:23 -07:00
e83b3d2472
turn up generator memory timeout
2016-06-29 10:57:31 -07:00
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
