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Commit Graph

4791 Commits

Author SHA1 Message Date
Yunsup Lee
c810847761 hookup all memory ports 2013-11-05 17:12:25 -08:00
Yunsup Lee
4c56323f6f hookup all memory ports 2013-11-05 17:12:09 -08:00
Stephen Twigg
3cdfde9861 Push hwacha, rocket 2013-11-05 15:31:59 -08:00
Stephen Twigg
eae571e371 Remove rocc memory simplifye module (Hwacha has its own) 2013-11-05 15:31:03 -08:00
Stephen Twigg
7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
Yunsup Lee
04108270ff push riscv-tools 2013-10-29 22:54:00 -07:00
Andrew Waterman
a875233be6 update subrepos 2013-10-29 21:17:07 -07:00
Andrew Waterman
3c1d1f7981 Fix(?) SBT race by defining subproject build order 2013-10-29 13:27:36 -07:00
Andrew Waterman
8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
Andrew Waterman
c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
Andrew Waterman
12f0369e6e Simplify divide early out circuitry 2013-10-29 13:20:40 -07:00
Andrew Waterman
b44dafbdca Simplify branch offset mux 2013-10-29 13:20:40 -07:00
Andrew Waterman
23f7bab4f3 Reduce FMA pipeline depths
FMA QoR has improved enough to allow this change.
2013-10-29 13:20:40 -07:00
Yunsup Lee
f440df5338 rename M_FENCE to M_NOP 2013-10-28 22:37:41 -07:00
Yunsup Lee
1583560757 fix replay bug, don't respond when cmd is a NOP 2013-10-28 22:35:18 -07:00
Stephen Twigg
437f7ed4af Push hardfloat (ignore target files) 2013-09-26 20:51:19 -07:00
Henry Cook
fc9c676fc1 add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
Henry Cook
42693d43ad simplify build.sbt 2013-09-26 09:51:14 -07:00
Stephen Twigg
f6d7e22c46 Push rocket (fix issue with uppermost bit of D$ req tag getting lost) 2013-09-25 11:52:01 -07:00
Stephen Twigg
36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. 2013-09-25 11:51:10 -07:00
Stephen Twigg
36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. 2013-09-25 01:21:41 -07:00
Stephen Twigg
891e459625 Export stats pcr register (#28 currently) to the top-level 2013-09-25 01:16:32 -07:00
Stephen Twigg
eb7e6f03b3 push rocket (AccumulatorExample fixes and documentation) 2013-09-24 16:33:32 -07:00
Stephen Twigg
730a6ec76b AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample 2013-09-24 16:32:49 -07:00
Stephen Twigg
472b947fbe push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory) 2013-09-24 16:16:12 -07:00
Stephen Twigg
eb03f61058 Properly ignore target files. Push uncore (properly ignore target files) 2013-09-24 16:03:28 -07:00
Stephen Twigg
20246b373e Properly ignore target files 2013-09-24 16:02:00 -07:00
Andrew Waterman
81c752de84 Support disabling virtual memory 2013-09-24 13:58:47 -07:00
Andrew Waterman
adc386f889 Turn off virtual memory inside RoCC base class 2013-09-24 13:58:47 -07:00
Stephen Twigg
081fcc4e63 push rocket (accelerator interface fixes) 2013-09-24 10:55:22 -07:00
Stephen Twigg
3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). 2013-09-24 10:54:09 -07:00
Stephen Twigg
fba0ae0fec Push rocket 2013-09-23 00:26:27 -07:00
Stephen Twigg
db1e09f0d0 Fix issues with RoCC AccumulatorExample stalls on memory interface 2013-09-23 00:21:43 -07:00
Stephen Twigg
324a6321bd Push tools (improve consistency: these tools will compile/test the new ISA encoding) 2013-09-22 03:24:11 -07:00
Stephen Twigg
2676ea8279 Push rocket (fix some issues with RoCC although some remain) 2013-09-22 03:19:43 -07:00
Stephen Twigg
158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) 2013-09-22 03:18:06 -07:00
Andrew Waterman
b7d7ced41b Update to new ISA 2013-09-21 06:40:23 -07:00
Andrew Waterman
1d2f4f8437 New ISA encoding, AUIPC semantics 2013-09-21 06:32:40 -07:00
Huy Vo
09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Huy Vo
c9813603ee Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 2013-09-19 20:11:11 -07:00
Huy Vo
cc3dc1bd0f bug fix 2013-09-19 20:10:56 -07:00
Andrew Waterman
9bf10ae5d2 remove extraneous toBits (need new Chisel) 2013-09-19 15:26:36 -07:00
Andrew Waterman
42970c9a99 Update Rocket 2013-09-15 04:39:52 -07:00
Andrew Waterman
25ab402932 swap JAL, JALR encodings 2013-09-15 04:29:06 -07:00
Andrew Waterman
628745226c Use spike disassembler riscv-dis if it exists 2013-09-15 04:25:53 -07:00
Andrew Waterman
80003b3019 Support RoCC 2013-09-15 04:25:26 -07:00
Andrew Waterman
110e53cb48 Revert "Add early out to multiplier"
This broke recently and I don't have time to figure out why.
2013-09-15 04:15:32 -07:00
Andrew Waterman
88d1c47665 don't disassemble within chisel 2013-09-15 04:14:45 -07:00
Andrew Waterman
f12bbc1e43 working RoCC AccumulatorExample 2013-09-14 22:34:53 -07:00
Andrew Waterman
18968dfbc7 Move store data generation into cache 2013-09-14 16:15:07 -07:00