riscv/rocket-chip
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1807 Commits

Author SHA1 Message Date
Stephen Twigg 6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. 2013-09-09 14:31:18 -07:00
Yunsup Lee ba9bbc27df apply same change to fpga top-level 2013-08-24 15:50:03 -07:00
Yunsup Lee 76cd90fc01 parameterize number of SCRs 2013-08-24 15:47:42 -07:00
Yunsup Lee 0884bc9789 fix DRAMSideLLCNull entries 2013-08-24 13:20:38 -07:00
Yunsup Lee 1e3ac0afa9 back to NTILES=1 2013-08-24 13:10:30 -07:00
Henry Cook b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
Henry Cook 85e5ce046f pulled submodule commits, uncore sbt standardized 2013-08-15 17:07:13 -07:00
Henry Cook 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 
Conflicts:
	chisel
	riscv-hwacha
	riscv-rocket
	uncore
 2013-08-15 16:39:30 -07:00
Henry Cook 784e017bae Final Reg standardization 2013-08-15 16:37:58 -07:00
Henry Cook 9b70ecf546 Reg standardization 2013-08-13 17:53:19 -07:00
Huy Vo cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Henry Cook 11e131af47 initial attempt at upgrade 2013-08-12 10:46:22 -07:00
Henry Cook 199e76fc77 Fold uncore constants into TileLinkConfiguration, update coherence API 2013-08-02 16:31:27 -07:00
Henry Cook 4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
Henry Cook 2796de01bf new tilelink arbiter types, reduced release xact trackers 2013-07-09 15:41:27 -07:00
Henry Cook 896179cbb6 removed bad mt test 2013-06-14 00:14:18 -07:00
Henry Cook c06cbf523b Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore. 2013-05-23 15:26:20 -07:00
Henry Cook 6a69d7d7b5 pass closure to generate bank addr 2013-05-23 14:58:19 -07:00
Andrew Waterman d825c9d6e9 make fpga Makefile work with updated Makefrag 2013-05-02 05:09:45 -07:00
Andrew Waterman cfa86dba4f add FPGA test bench 
The memory models now support back pressure on the response.
 2013-05-02 04:59:32 -07:00
Andrew Waterman 50bd9a08a7 resynchronize fpga uncore 2013-05-01 01:12:47 -07:00
Yunsup Lee 93df795e48 change LLC leaf SRAM size 2013-04-22 11:06:50 -07:00
Huy Vo 2ac3fd5306 get rid of init_node 2013-04-20 01:36:32 -07:00
Huy Vo 0d87e3bacc fixed init pin generation 2013-04-20 00:38:01 -07:00
Henry Cook a01cdf95fd tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps 2013-04-10 13:53:27 -07:00
Henry Cook 16ad8a7e9c Fixes after merge 2013-03-25 19:14:38 -07:00
Andrew Waterman 8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook eec590c1bf Added support for multiple L2 banks. Moved tile IO queueing. 2013-03-25 17:01:46 -07:00
Henry Cook 806f897fc4 nTiles -> nClients in LogicalNetworkConfig 2013-03-25 17:01:46 -07:00
Andrew Waterman ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Henry Cook cf76665d09 writebacks on release network pass asm tests and bmarks 2013-03-25 17:01:46 -07:00
Henry Cook a0dc8d52d6 using new network and l2 controller 2013-03-25 17:01:46 -07:00
Yunsup Lee 9efe71412f add DRAMSideLLCNull 2013-03-19 00:43:34 -07:00
Andrew Waterman 4077b22929 include fesvr as a library; improve harnesses 2013-01-24 23:57:23 -08:00
Yunsup Lee 516a64f576 commit vec=true 2013-01-22 20:24:33 -08:00
Henry Cook bb5c465bb3 Switched back to old, better-tested hub on master 2013-01-22 19:57:31 -08:00
Henry Cook 5b82d72eb7 New TileLink bundle names 2013-01-21 17:19:07 -08:00
Henry Cook 72bba81a76 now using single-ported coherence master 2013-01-16 23:58:24 -08:00
Henry Cook e33648532b Refactored packet headers/payloads 2013-01-15 15:57:06 -08:00
Henry Cook a922b60152 Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor 2013-01-07 14:23:49 -08:00
Henry Cook f2cef8d8d2 new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore 2013-01-07 14:19:55 -08:00
Andrew Waterman fd727bf8aa add some of the zedboard fpga infrastructure 
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
 2013-01-06 03:58:10 -08:00
Henry Cook d0805359a5 Refactored uncore conf 2012-12-13 11:46:29 -08:00
Henry Cook 1d7f1a8182 Removed dummy tile instances 2012-12-12 16:44:03 -08:00
Henry Cook 0e73cc8c12 Removed dummy tile instances 2012-12-12 16:41:21 -08:00
Henry Cook 177909c955 Initial version of phys/log network compiles 2012-12-12 11:15:10 -08:00
Henry Cook be4e5b8327 Initial version of phys/log network compiles 2012-12-12 00:06:14 -08:00
Andrew Waterman e12af07722 update to newest rocket 2012-11-25 04:40:46 -08:00
Yunsup Lee 4d73e6e38a revamp vector yet again with new D$ 2012-11-18 03:14:22 -08:00
Andrew Waterman b58214d7e3 remove more global constants 2012-11-17 17:25:43 -08:00