riscv/rocket-chip
1
0
Fork 0
Code Releases Activity
4,942 Commits 1 Branch 0 Tags
e945f6e2656239308dc2c0dadc9e3ffc32969bdb
Commit Graph
100 Commits
This Branch
This Branch
All Branches
Author SHA1 Message Date
Wesley W. TerpstraandGitHub f191bb994c PatternPusher: can now expect a certain output (#952) 2017-08-11 18:10:27 -07:00
Wesley W. TerpstraandGitHub baf769f924 tilelink: add PatternPusher, a device to inject a fixed traffic pattern (#950) 2017-08-11 15:07:10 -07:00
Wesley W. TerpstraandGitHub fa867bc478 plusarg_reader: make synthesis path a no brainer (#947) 2017-08-10 16:35:30 -07:00
Wesley W. TerpstraandGitHub 49ba31ac34 Merge pull request #942 from freechipsproject/bus-blocker-lock 
Bus blocker lock
 2017-08-08 18:03:36 -07:00
Wesley W. Terpstra a9b1410f01 BusBlocker: parameterize page granularity 2017-08-08 17:10:01 -07:00
Wesley W. Terpstra 010ba94474 BusBlocker: rename a variable 2017-08-08 17:00:22 -07:00
Wesley W. Terpstra 6d6fc38787 BusBlocker: lock bit should affect the prior PMP address, not next 2017-08-08 17:00:12 -07:00
Wesley W. TerpstraandGitHub 3ef6e4c9f2 Merge pull request #939 from freechipsproject/bus-blocker 
tilelink: PMP controlled BusBlocker prevents bus accesses
 2017-08-08 15:06:55 -07:00
Wesley W. Terpstra 8f261adc6b BusBlocker: change default policy to deny 2017-08-08 14:19:59 -07:00
Wesley W. Terpstra 0d76e96b88 tilelink: PMP controlled BusBlocker prevents bus accesses 2017-08-08 13:28:01 -07:00
Wesley W. TerpstraandGitHub e27072e063 Merge pull request #931 from freechipsproject/fix-ram-model-source-reuse 
Fix ram model source reuse
 2017-08-07 16:56:13 -07:00
Wesley W. Terpstra d5a135914b Revert "Disable AMBAUnitTestConfig, as it is blocking unrelated PRs" 
This reverts commit 39b7e930ca.

Now that the RAMModel can properly tolerate overlapping responses
in the face of source reuse, we can re-enable the regression test.
 2017-08-07 16:04:02 -07:00
Wesley W. Terpstra f8b45564d1 tilelink: RAMModel must support source reuse 
If a multibeat response comes back, the source might be reused.
If response reordering has made the multibeat response invalid,
we need to remember this even if the valid bit is cleared on reuse.
 2017-08-07 16:01:15 -07:00
Wesley W. TerpstraandGitHub d03fdc4f30 diplomacy: seal the LazyModuleImpLike trait (#927) 
This makes sure that all the base classes call instantiate()
 2017-08-06 17:32:23 -07:00
Wesley W. TerpstraandGitHub 42ff74bd34 Merge pull request #910 from freechipsproject/tilelink-map 
Tilelink map
 2017-07-31 18:33:09 -07:00
Wesley W. Terpstra d7fd9d2b82 tilelink: Filter, add another case 2017-07-31 16:51:26 -07:00
Wesley W. Terpstra b126105230 tilelink: add TLMap to make it possible to move slaves 2017-07-31 16:39:00 -07:00
Wesley W. Terpstra 13d3ffbcaa tilelink: Filter now support arbitrary filter functions 2017-07-31 16:38:38 -07:00
Wesley W. TerpstraandGitHub 8e2e931770 Merge pull request #903 from freechipsproject/monitor-probes 
tilelink: use the Monitor to enforce Probe sourcing
 2017-07-29 01:12:08 -07:00
Wesley W. Terpstra 56e28026a6 TLError: does not need to be fast; cut the loop 
The SystemBus already has a flow buffer on outputs.
 2017-07-29 00:22:21 -07:00
Wesley W. Terpstra 540256e24a systembus: all slaves should have an output buffer 2017-07-29 00:13:33 -07:00
Wesley W. Terpstra eadf4e9fcc Revert "tile: add option for tile boundary buffers" 
This reverts commit b64b87ad07.

The crossings already have buffering in those places where it was
appropriate. Adding more does not help flow through paths.
 2017-07-29 00:03:24 -07:00
Wesley W. Terpstra 68064ba260 systembus: don't double down on buffers 
The order should be:
  master => buffer|xing => fifofixer => splitter => xbar
 2017-07-29 00:02:12 -07:00
Wesley W. Terpstra a0db929003 tilelink: use the Monitor to enforce Probe sourcing 2017-07-28 18:08:00 -07:00
Wesley W. TerpstraandGitHub 370cc392e0 Merge pull request #898 from freechipsproject/uncached-acquire 
tilelink: it is now legal to support Acquire for UNCACHED regions
 2017-07-27 22:14:53 -07:00
Wesley W. Terpstra 5f81c2243f tilelink: add BusBypass, useful to turn devices off 2017-07-27 20:16:30 -07:00
Wesley W. Terpstra 9a36755b6a tilelink: CacheCork uses constructor helpers 2017-07-27 18:38:15 -07:00
Wesley W. Terpstra 45189c3e30 tilelink: CacheCork now supports errors and BtoT upgrade 
- Acquire.BtoT succeeds with toT instantly
- AccessAckData.error causes Grant.toN.error
 2017-07-27 18:38:13 -07:00
Wesley W. Terpstra 2e4f1611ed tilelink: Error device supports Acquire 
We need this if we want to divert traffic to it from a TL-C slave.
 2017-07-27 18:32:58 -07:00
Wesley W. Terpstra 651da73d89 tilelink: it is now legal to support Acquire for UNCACHED regions 
These cases exist:
  GET_EFFECTS, PUT_EFFECTS, UNCACHEABLE && !supportsAcquire: MMIO
  UNCACHED && !supportsAcquire: speculation ok and may be cached
  UNCACHED && supportsAcquire: LLC/CacheCork applied (slave never probes)
  CACHED, TRACKED && supportsAcquire: slave might probe
 2017-07-27 11:11:22 -07:00
Wesley W. TerpstraandAndrew Waterman 0ab5cb67b3 tilelink: fix RAMModel handling of AMOs on early source reuse (#897) 2017-07-27 11:07:13 -07:00
Wesley W. TerpstraandGitHub 9804bdc34e tilelink: remove obsolete addr_lo signal (#895) 
When we first implemented TL, we thought this was helpful, because
it made WidthWidgets stateless in all cases. However, it put too
much burden on all other masters and slaves, none of which benefitted
from this signal. Furthermore, even with addr_lo, WidthWidgets were
information lossy because when they widen, they have no information
about what to fill in the new high bits of addr_lo.
 2017-07-26 16:01:21 -07:00
Wesley W. TerpstraandGitHub 3cceb866cf Merge pull request #896 from freechipsproject/fuzzer-rage 
Fuzzer rage
 2017-07-26 16:01:07 -07:00
Wesley W. Terpstra d096d5d1c4 tilelink: fix AtomicAutomata bug wrt early source reuse 
The new fuzzer already found it's first victim.
 2017-07-26 12:52:29 -07:00
Wesley W. Terpstra 6550ae2e31 tilelink: increase Fuzzer source reuse aggression 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra 1efdca106c tilelink: RAMModel support early reuse of source 2017-07-26 12:37:31 -07:00
Wesley W. Terpstra 138276fd87 tilelink: SourceShrinker should work also for 0 latency 2017-07-26 12:37:31 -07:00
Wesley W. TerpstraandGitHub f02c921d0f Merge pull request #893 from freechipsproject/width-update 
Width widget enhancements
 2017-07-26 12:35:51 -07:00
Wesley W. Terpstra b2edca2a6b tilelink: cut WidthWidget from dependency on addr_lo 2017-07-26 10:31:09 -07:00
Wesley W. Terpstra ede87c1f73 tilelink: rewrite WidthWidget beat splitter 
- split the data based on the address, not the mask
  (the first version of TileLink did not have low address bits)
- the dependency on addr_lo is now exposed and easy to replace
 2017-07-26 10:24:16 -07:00
Wesley W. Terpstra 0f5065fbf3 tilelink: WidthWidget rewrite beat merging 
- errors are properly OR reduced
- registers latched only as needed (was previously a shift register)
- combines beats without inspecting address (removes addr_lo dependency)
 2017-07-26 10:24:12 -07:00
Wesley W. TerpstraandGitHub f0ffb7e31e tilelink: initialize toggle in Fragmenter (#894) 
No strictly necessary, because the initial value does not matter, but good hygiene since it drives a cycle of logic.
 2017-07-26 10:21:31 -07:00
Wesley W. TerpstraandGitHub c2b8b08461 tilelink: fix Fragmenter source re-use bug (#888) 
Consider the following waveform for two 4-beat bursts:
---A----A------------
-------D-----DDD-DDDD
Under TL rules, the second A can use the same source as the first A,
because the source is released for reuse on the first response beat.

However, if we fragment the requests, it looks like this:
---3210-3210---------
-------3-----210-3210
... now we've broken the rules because 210 are twice inflight.

To solve this, we alternate an a.source bit every time D completes a txn.
 2017-07-25 16:23:55 -07:00
Wesley W. TerpstraandGitHub 68ed055f6d chiplink: adjust bus view to include the splitter (#886) 2017-07-24 21:41:17 -07:00
Wesley W. TerpstraandGitHub 8d793daf9c Merge pull request #876 from freechipsproject/sq-helper 
ShiftQueue: support constant propagation
 2017-07-18 16:30:23 -07:00
Wesley W. Terpstra a9c58e9d9f diplomacy: support creating ShiftQueues as well 2017-07-18 14:57:02 -07:00
Wesley W. Terpstra c0a3bb58e9 ShiftQueue: use Vec of Bool to support constant prop of enq.valid 2017-07-18 14:56:59 -07:00
Wesley W. TerpstraandGitHub 416629b3bf tilelink: FIFOFixer should fix no domain => domain cases (#873) 2017-07-17 22:32:17 -07:00
Wesley W. TerpstraandGitHub d09a985729 zero: fix attachment in multichannel case (#870) 2017-07-17 21:48:31 -07:00
Wesley W. TerpstraandGitHub fc75ada577 tilelink: Monitor should report line numbers of connection that failed (#872) 2017-07-17 21:29:14 -07:00
Wesley W. TerpstraandGitHub 16e8709144 tilelink: it is now legal to have errors on {Release,Hint}Ack (#864) 2017-07-14 16:13:30 -07:00
Wesley W. TerpstraandGitHub b7f1ba3428 tilelink: FIFOFixer must support null cases (#860) 
In particular, it is ok if no slaves actually need FIFO fixing.
It is also ok if none of those fixed are FIFO.
 2017-07-12 22:20:31 -07:00
Wesley W. TerpstraandGitHub 0053a060ae Merge pull request #859 from freechipsproject/fifo-fixer-configable 
Fifo fixer configable
 2017-07-12 19:44:23 -07:00
Wesley W. Terpstra 4eface8a9e rocket: do not require FIFO order for memory-like regions 2017-07-12 17:39:00 -07:00
Wesley W. Terpstra 09b9d33a9a tilelink: FIFOFixer now has a policy parameter 2017-07-12 17:38:55 -07:00
Wesley W. Terpstra b363a94480 diplomacy: add a new UNCACHEABLE RegionType 2017-07-12 16:31:50 -07:00
Wesley W. Terpstra c8a7648169 diplomacy: only evaluate a Nexus node's map function once 2017-07-12 16:20:55 -07:00
Wesley W. TerpstraandGitHub af3976aa67 regmapper: add byte-sized RegField helper function (#854) 2017-07-10 21:08:02 -07:00
Wesley W. TerpstraandGitHub 29f5f77817 Merge pull request #853 from freechipsproject/sram-errors 
SRAM errors
 2017-07-07 22:44:28 -07:00
Wesley W. Terpstra 5db0e770d5 tilelink: TestSRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 702143eb33 tilelink: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 9310a33e77 apb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:40 -07:00
Wesley W. Terpstra 28fbf1af8e ahb: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra df44b23956 axi4: SRAM can emulate incompletely populated memory 2017-07-07 21:40:39 -07:00
Wesley W. Terpstra b2cc4b99ed tilelink: TestSRAM reports errors on illegal access 2017-07-07 21:40:36 -07:00
Wesley W. Terpstra e8cb6dafd3 tilelink: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra f1fb3be603 ahb: SRAM reports errors on illegal access 2017-07-07 21:15:36 -07:00
Wesley W. Terpstra 19851a7c9e apb: SRAM reports errors on illegal access 2017-07-07 21:15:33 -07:00
Wesley W. TerpstraandGitHub 025f7d890b axi4: SRAM now reports errors on illegal address (#852) 2017-07-07 19:27:32 -07:00
Wesley W. TerpstraandGitHub 367d4aebe6 Set complete unconditionally 2017-06-30 10:15:53 -07:00
Wesley W. TerpstraandGitHub 4e9f65b2ef Simplify logic further and bugfix 
complete was being set unconditionally
 2017-06-30 10:07:39 -07:00
Wesley W. TerpstraandGitHub 3dca2bc4a3 gah 2017-06-30 01:07:29 -07:00
Wesley W. TerpstraandGitHub e43b7accf9 Fix compile error and eliminate wasteful wires 2017-06-30 01:06:02 -07:00
Wesley W. TerpstraandGitHub e3c7bb3b1f SRAM: MemoryDevices use .reg (not .reg("mem")) (#835) 2017-06-29 19:07:12 -07:00
Wesley W. TerpstraandGitHub 7dae3388e1 Merge pull request #830 from freechipsproject/flip-dts-idtim 
Flip dts itim and dtim references
 2017-06-29 00:18:19 -07:00
Wesley W. Terpstra 5edc4546e3 rocket: add dtim and itim refs to cpus 2017-06-28 23:10:58 -07:00
Wesley W. Terpstra 7d6f8d48f2 Revert "rocket: link dtim to its cpu" 
This reverts commit e6c2d446cc.
 2017-06-28 23:10:57 -07:00
Wesley W. Terpstra fbcd6f0eb2 Revert "rocket: link itim to its cpu" 
This reverts commit 48390ed604.
 2017-06-28 23:10:57 -07:00
Wesley W. TerpstraandGitHub 5002d2accf Merge pull request #827 from freechipsproject/dts-improvements 
Dts improvements
 2017-06-28 17:45:06 -07:00
Wesley W. Terpstra 66489ffa13 rom+sram: add a compatible field 2017-06-28 15:41:20 -07:00
Wesley W. Terpstra ca3030cba3 dcache: fix a gender inversion bug introduced in #826 2017-06-28 15:38:53 -07:00
Wesley W. Terpstra 02aa80a958 TLZero: include a version number 2017-06-28 15:12:46 -07:00
Wesley W. Terpstra 48390ed604 rocket: link itim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra e6c2d446cc rocket: link dtim to its cpu 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 3f6d5110cd rocket: dtim is not a dcache 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra bca3db0866 diplomacy: add RWXC permissions also to ResourceMappings 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 5436be54ff periphery: use SimpleBus for mmio ports 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 171e1a4c05 diplomacy: add SimpleBus to describe bridges 2017-06-28 15:06:19 -07:00
Wesley W. Terpstra 84dc23c215 devices: add reg-names to most devices 2017-06-28 15:06:16 -07:00
Wesley W. Terpstra 0bf46edb6c diplomacy: support reg-names in DTS output 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra 852f03282f rocket: give itim and dtim a compatible field for drivers to match 2017-06-28 14:26:55 -07:00
Wesley W. Terpstra 6c2b770605 plic: do not output #address-cells 
This is only needed for an interrupt-map, not an interrupt-controller.
 2017-06-28 14:26:55 -07:00
Wesley W. TerpstraandGitHub 66f64a9759 tilelink2 ToAXI4: don't interlock R+W for non-FIFO masters (#822) 
idCount <= 1 implies that no more than one transaction can be inflight,
so there is no need to interlock R+W. However, when stripBits > 0, it is
possible for a non-FIFO master to have > 1 idCount. In this case, we
also don't need to interlock R+W.
 2017-06-26 17:54:17 -07:00
Wesley W. TerpstraandGitHub 7a0655ae88 Merge pull request #816 from freechipsproject/reduce-axi-queues 
Reduce AXI4 queues
 2017-06-23 18:31:41 -07:00
Wesley W. Terpstra 8ca6c10994 tilelink2: ToAXI4 can strip off low source ID bits 
Some TL converters place extra meta data in the low bits of source.
Examples include the TLFragmenter and CacheCork.

This new argument makes it possible to save AXI4 ID space by reclaiming
those bits upon conversion.
 2017-06-23 17:22:45 -07:00
Wesley W. Terpstra feecfb53ed axi4: Deinterleaver need not make a Q for an unused AXI id 2017-06-23 17:22:42 -07:00
Wesley W. TerpstraandGitHub 9bea7c1c58 Merge pull request #815 from freechipsproject/reduce-others 
Reduce others
 2017-06-23 12:13:48 -07:00
Wesley W. Terpstra 2d8b2f4edd ReduceOthers: remove constants from the balanced AND tree 2017-06-23 00:28:05 -07:00
Wesley W. Terpstra 48611266fa diplomacy: use ReduceOthers in the RegMapper 2017-06-22 19:43:47 -07:00
Wesley W. Terpstra 11d1cb02eb util ReduceOthers produces nlogn cost ready-valid logic 2017-06-22 19:43:20 -07:00