riscv/rocket-chip
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74 Commits

Author SHA1 Message Date
Andrew Waterman
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Yunsup Lee
4afc9c69a0 streamline sbt 2016-04-19 14:22:22 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Howard Mao
85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
Palmer Dabbelt
95b065153d Add CDE to the submodule list 
Without this I don't get rebuilds when toching a file in CDE.
 2016-02-17 15:23:25 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Palmer Dabbelt
1149a412cc Support make-3.82 and newer 
make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests".  This patch changes the hex file
rules to ensure they match between the two versions of make.

I've tried this with both make-3.81 and make-4.1, and they both work for me.
 2016-01-28 12:19:11 -08:00
Jim Lawson
c5e9558571 Double Java MaxPermSize. 2015-12-07 12:05:06 -08:00
Howard Mao
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Colin Schmidt
6f85ed191e Add rocketchip_addons to the list of chisel srcs requiring rebuild 2015-09-16 12:28:03 -07:00
Ben Keller
8e9c15c10d If you don't have spike-disasm in your path, your path is dumped 
to stdout by this line every time you do anything in the entire repo.
 2015-09-03 15:36:11 -07:00
Scott Beamer
333c594d2a respect environment's CXX 2015-08-25 13:26:14 -07:00
Andrew Waterman
34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Henry Cook
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals). 
Bump all submodules.
 2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used 2015-07-28 00:24:07 -07:00
Henry Cook
866396545d For vlsi, make Memdessert elaborate before Top so the generated Makefrag-tests doesn't get overwritten 2015-07-23 17:00:22 -07:00
Yunsup Lee
caf89baeb7 update zscale 2015-07-23 13:59:45 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Yunsup Lee
d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Yunsup Lee
09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00
Henry Cook
854fd64fba Added optional Makefile includes for private chip repos 2015-07-06 17:15:27 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Yunsup Lee
7a28d2b47c forgot to move more hwacha stuff out in rocket-chip 2014-09-25 15:34:18 -07:00
Yunsup Lee
275b72368b add CONFIG to the name of simulator executable 2014-09-11 22:11:58 -07:00
Yunsup Lee
086bb02c24 check RISCV envirnoment variable 2014-09-11 02:38:21 -07:00
Yunsup Lee
02c08a156f generate consts.vh from chisel source 2014-09-10 17:14:55 -07:00
Yunsup Lee
cfecd8832d tease out reference-chip specific stuff 2014-09-09 20:49:28 -07:00
Yunsup Lee
ddfd3ce968 further generalize fpga/vlsi builds 2014-09-08 00:21:57 -07:00
Henry Cook
82467313dd merge in rocketchip changes from master 2014-09-02 13:51:57 -07:00
Yunsup Lee
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
Adam Izraelevitz
fcd68364ff Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	src/main/scala/ReferenceChip.scala
 2014-08-01 18:07:22 -07:00
Henry Cook
1bf5439f0b include new mm test in benchmarks 2014-04-18 18:05:30 -07:00
Andrew Waterman
f04bde75fb New FP encoding 2014-03-11 19:12:20 -07:00
Yunsup Lee
23045ec379 add hwacha vfmsv instructions, keepcfg bug fix, turn off secondary fconv 2014-03-02 03:38:06 -08:00
Yunsup Lee
bcfcdefe88 update hwacha 2014-02-27 04:39:12 -08:00
Yunsup Lee
46714c0c60 more improvements to hwacha 2014-02-26 21:20:53 -08:00
Yunsup Lee
a5625de3d5 support vector irq tests 2014-02-25 21:18:03 -08:00
Yunsup Lee
e5c2bd5e7b add extensions option to riscv-dis for better disassembly 2014-02-25 03:50:32 -08:00
Adam Izraelevitz
58d2e62e3f Merge branch 'master' of github.com:ucb-bar/reference-chip into dse 
Conflicts:
	chisel
	src/main/scala/ReferenceChip.scala
 2014-02-19 14:24:36 -08:00
Stephen Twigg
6808245bb5 Timeout cycles now defined in toplevel Makefrag in order to allow for easier alteration when debugging. 2014-02-12 16:50:13 -08:00
Adam Izraelevitz
548cf16061 Added jack Makefile and hammer.scala, as well as changed reference chip to have multiple datacache sizes. Requires chisel branch dse 2014-02-11 14:36:47 -08:00
Yunsup Lee
dbeadba2dc add vfmvv 2014-02-05 03:28:33 -08:00