29600f64ec
make memsize configurable
2016-08-17 16:31:34 -07:00
ed827678ac
Write test harness in Chisel
...
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected). However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary. Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.
This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence. The main blocker is the lack of Verilog parameterization for
BlackBox. It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL. But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
47a0c880a4
make sure TLId set in Periphery
2016-08-15 13:58:23 -07:00
e939af88aa
explicitly set TLId for bus TL ports
2016-08-15 12:46:29 -07:00
2c39f039b5
make external address map order overrideable
2016-08-15 11:40:28 -07:00
fb476d193c
refactor main App for better code re-use
2016-08-11 16:15:23 -07:00
e0ae039235
fix config string generation for extra devices
2016-08-11 10:44:32 -07:00
647dbefd9b
split coreplex off into separate package
2016-08-10 18:04:22 -07:00
4bfa7ceb6a
unit tests in Coreplex instead of Tile
2016-08-10 11:26:14 -07:00
0ee1ce4366
separate Coreplex and TopLevel parameter traits
2016-08-10 09:49:56 -07:00
f95d319162
don't use secondary external address map; collapse submap instead
2016-08-09 22:29:38 -07:00
2645f74af2
clean up addrmap flatten function
2016-08-09 22:14:32 -07:00
33f13d5c49
don't repeat external addr map base
2016-08-09 21:20:54 -07:00
3ea2f4a6c4
refactor top-level into coreplex and platform
2016-08-09 18:26:52 -07:00
dd1fed41b6
generate BootROM contents from assembly code
2016-08-05 16:39:21 -07:00
9fa5b228b2
allow extra devices and top-level ports to be added without changing RocketChip.scala
2016-08-04 14:06:14 -07:00
410e3e5366
make sure TraceGen gets correct addresses
2016-08-04 11:08:25 -07:00
0a85e92652
Allow additional internal MMIO devices to be created without changing BaseConfig
2016-08-04 11:04:52 -07:00
f04aefc95c
get rid of deprecated ZynqAdapter
2016-08-02 13:14:20 -07:00
63b814fcd7
only run the important (high coverage) tests in regression suite
2016-08-02 10:54:05 -07:00
b7723f1ff8
make unit tests local to the packages being tested
2016-08-01 17:02:00 -07:00
98eede0505
some refactoring in RocketChip top-level
2016-08-01 17:02:00 -07:00
55c992bb3a
Use FoldRight() instead of for loop
2016-08-01 16:56:33 -07:00
8db2e8829f
Allow aggregate CONFIG on Command Line
2016-08-01 14:24:16 -07:00
fe670e5421
Stop using deprecated FileSystemUtilities to create files
2016-07-31 18:04:56 -07:00
058396aefe
[rocket] Implement RVC
2016-07-29 17:56:42 -07:00
cb86aaa46b
fix trace generator addresses
2016-07-28 17:56:14 -07:00
ecd1af326c
fix L2 deadlock bug and add more advanced trace generator
2016-07-26 12:43:08 -07:00
1063d90993
make sure L1 and L2 agree on coherence policy
2016-07-25 12:20:49 -07:00
6a5b2d7f59
fix assembly tests for configurations without VMU and/or user mode
2016-07-22 17:21:57 -07:00
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
