generate BootROM contents from assembly code

src/main/scala/Configs.scala

@@ -315,6 +315,7 @@ class BaseConfig extends Config (
           dataBeats = innerDataBeats,
           dataBits = site(CacheBlockBytes) * 8)
       }
+      case BootROMFile => "./bootrom/bootrom.img"
       case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
       case NTiles => Knob("NTILES")
       case AsyncMemChannels => false

src/main/scala/RocketChip.scala

@@ -13,6 +13,8 @@ import uncore.util._
 import uncore.converters._
 import rocket._
 import rocket.Util._
+import java.nio.{ByteBuffer,ByteOrder}
+import java.nio.file.{Files, Paths}
 
 /** Top-level parameters of RocketChip, values set in e.g. PublicConfigs.scala */
 
@@ -56,6 +58,7 @@ case object PLICKey extends Field[PLICConfig]
 /** Number of clock cycles per RTC tick */
 case object RTCPeriod extends Field[Int]
 case object AsyncDebugBus extends Field[Boolean]
+case object BootROMFile extends Field[String]
 
 /** Utility trait for quick access to some relevant parameters */
 trait HasTopLevelParameters {
@@ -271,25 +274,19 @@ class Uncore(implicit val p: Parameters) extends Module
   }
 
   def makeBootROM()(implicit p: Parameters) = {
-    val rom = java.nio.ByteBuffer.allocate(32)
-    rom.order(java.nio.ByteOrder.LITTLE_ENDIAN)
+    val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
+    val rom = ByteBuffer.wrap(romdata)
+
+    rom.order(ByteOrder.LITTLE_ENDIAN)
 
     // for now, have the reset vector jump straight to memory
     val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector)
     require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
     val configStringAddr = p(ResetVector).toInt + rom.capacity
 
-    // This boot ROM doesn't know about any boot devices, so it just spins,
-    // waiting for the debugger to load a program and change the PC.
-    rom.putInt(0x0000006f)                        // loop forever
-    rom.putInt(0)                                 // reserved
-    rom.putInt(0)                                 // reserved
-    rom.putInt(configStringAddr)                  // pointer to config string
-    rom.putInt(0)                                 // default trap vector
-    rom.putInt(0)                                 //   ...
-    rom.putInt(0)                                 //   ...
-    rom.putInt(0)                                 //   ...
-
+    require(rom.getInt(12) == 0,
+      "Config string address position should not be occupied by code")
+    rom.putInt(12, configStringAddr)
     rom.array() ++ p(ConfigString).toSeq
   }
 

src/main/scala/Testing.scala

@@ -4,7 +4,7 @@ package rocketchip
 
 import Chisel._
 import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
-import cde.{Parameters, ParameterDump, Config, Field}
+import cde.{Parameters, ParameterDump, Config, Field, CDEMatchError}
 
 case object RegressionTestNames extends Field[LinkedHashSet[String]]
 
@@ -203,8 +203,7 @@ object TestGenerator extends App {
     }
     currentConfig ++ finalConfig
   }
-
-  val world = (new Config(finalConfig)).toInstance
+  val world = finalConfig.toInstance
 
   val paramsFromConfig: Parameters = Parameters.root(world)