riscv/rocket-chip
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explicitly set TLId for bus TL ports

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This commit is contained in:
Howard Mao
2016-08-15 12:45:24 -07:00
parent 2c39f039b5
commit e939af88aa
2 changed files with 6 additions and 4 deletions
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src/main/scala/RocketChip.scala
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@ -52,6 +52,7 @@ trait HasTopLevelParameters {
lazy val nMemAXIChannels = if (tMemChannels == BusType.AXI) nMemChannels else 0
lazy val nMemAHBChannels = if (tMemChannels == BusType.AHB) nMemChannels else 0
lazy val nMemTLChannels = if (tMemChannels == BusType.TL) nMemChannels else 0
lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
lazy val exportBus = p(ExportBusPort)
@ -172,7 +173,7 @@ class Periphery(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {
val mem_in = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams)).flip
val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO) else None
val bus_out = if (exportBus) Some(new ClientUncachedTileLinkIO()(innerParams)) else None
val mmio_in = if (exportMMIO) Some(new ClientUncachedTileLinkIO()(outermostMMIOParams).flip) else None
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)