Henry Cook
1d76255dc1
new chisel version jar and find and replace INPUT and OUTPUT
2012-01-18 14:39:57 -08:00
Andrew Waterman
e4cf6391d7
fix i$ miss pathology and badvaddr bug
2012-01-17 23:47:35 -08:00
Andrew Waterman
0369b05deb
move replays to writeback stage
2012-01-17 21:12:31 -08:00
Andrew Waterman
1c8f496811
fix fpga build
2012-01-13 20:04:11 -08:00
Andrew Waterman
addfe55735
add FPGA memory generator script
2012-01-13 18:19:08 -08:00
Andrew Waterman
acf3134e80
minor control logic cleanup
2012-01-12 14:19:18 -08:00
Andrew Waterman
4807d7222b
use replay to handle I$ misses
...
this eliminates a long path in the fetch stage
2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350
remove icache req_rdy signal
2012-01-11 18:27:11 -08:00
Andrew Waterman
bcb55e581a
remove host.start signal, use reset instead
2012-01-11 17:49:32 -08:00
Andrew Waterman
92dda102b6
slight control logic cleanup
2012-01-11 16:56:40 -08:00
Andrew Waterman
938b142d64
require writes to memory to be uninterrupted
2012-01-03 18:41:53 -08:00
Andrew Waterman
142dfc6e07
made tohost/fromhost 64 bits wide
2012-01-03 15:09:08 -08:00
Andrew Waterman
20aee36c96
move PCR writes to WB stage
2012-01-02 15:42:39 -08:00
Andrew Waterman
3045b33460
remove second RF write port
...
load miss writebacks are treated like mul/div now.
2012-01-02 02:51:30 -08:00
Andrew Waterman
ffe23a1ee8
fix WAW hazard handling
2012-01-02 00:25:11 -08:00
Andrew Waterman
eb657dd250
reduce superfluous replays
...
we only replay after a cache miss if we mis-scheduled the use of a load.
2012-01-01 21:28:38 -08:00
Andrew Waterman
efc623cc36
validate BTB address and use BTB for J/JAL/JR/JALR
...
even if we weren't using the BTB for JR/JALR, we'd need to
flush the BTB on FENCE.I and on context switches, but
validating its result suffices instead.
2012-01-01 17:04:14 -08:00
Andrew Waterman
2f8fcebea0
remove datapath register resets resets
2012-01-01 16:09:40 -08:00
Andrew Waterman
f9160c53cf
fixes for correct verilog generation
2011-12-29 23:46:21 -08:00
Andrew Waterman
1028ff7d9b
fix multiplier bug
2011-12-29 23:45:09 -08:00
Andrew Waterman
d65e1a2eee
vlsi verilog compiles now but doesn't simulate
2011-12-20 22:08:27 -08:00
Andrew Waterman
38ea10a5f4
parameterized multiplier unrolling
2011-12-20 04:18:28 -08:00
Andrew Waterman
733fc8e65e
booth multiplier
2011-12-20 03:49:07 -08:00
Andrew Waterman
b5a8b6dc73
fix divider for RV32
2011-12-19 16:57:53 -08:00
Andrew Waterman
bcceb08373
add dummy mul_rdy signal
2011-12-17 07:30:47 -08:00
Andrew Waterman
96c78829b4
improve ALU and fix revealed emulator bug
2011-12-17 07:20:32 -08:00
Andrew Waterman
82700cad72
fix multiplier for rv32
2011-12-17 07:20:00 -08:00
Andrew Waterman
a8d0cd95e6
hellacache now works
2011-12-17 03:26:11 -08:00
Andrew Waterman
56c4f44c2a
hellacache returns!
...
but AMOs are unimplemented.
2011-12-12 06:49:39 -08:00
Yunsup Lee
0ea2704b80
new mftx instruction format
2011-12-12 03:23:12 -08:00
Andrew Waterman
8308345364
work in progress on hellacache
2011-12-10 07:01:47 -08:00
Andrew Waterman
ce201559f3
Support cache->cpu nacks one cycle after request
2011-12-10 00:42:09 -08:00
Andrew Waterman
c01e1f1cef
Don't replay from EX stage.
...
EX replays are now handled from MEM. We may move them to WB.
2011-12-09 19:42:58 -08:00
Andrew Waterman
218f63e66e
code cleanup/parameterization
2011-12-09 00:42:43 -08:00
Andrew Waterman
a87ad06780
Automatically infer rocketCAM address width
2011-12-06 02:05:40 -08:00
Rimas Avizienis
fa784d1d7d
made setReadLatency argument a parameter defined in consts.scala
2011-12-05 00:33:17 -08:00
Rimas Avizienis
ff95cacb55
icache/dcache tag+data arrays now implemented using Mem4()
...
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
2011-12-04 01:18:38 -08:00
Rimas Avizienis
e894b79870
caches now use Mem4() memories for tag+data arrays
2011-12-03 19:41:15 -08:00
Rimas Avizienis
c580180b66
tweaks to cache/SRAM interface for TSMC65 SRAMs
2011-12-02 02:01:08 -08:00
Rimas Avizienis
e70b41241c
changed branch addr generation to get it off critical path
2011-12-02 01:56:17 -08:00
Rimas Avizienis
cf1965493b
renamed SRAM modules to match TSMC65 MC generated SRAMs
2011-12-01 13:14:33 -08:00
Rimas Avizienis
da2fdf4f85
fixed console i/o
2011-11-30 22:51:59 -08:00
Rimas Avizienis
b2894671f6
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2011-11-30 21:55:13 -08:00
Rimas Avizienis
bc44572d99
bugfixes due to new hcl jar file
2011-11-30 21:54:55 -08:00
Andrew Waterman
8f3927fdfa
queue data type is now templated
2011-11-30 18:08:26 -08:00
Rimas Avizienis
11f0e3daf4
more cleanup
2011-11-18 00:17:30 -08:00
Rimas Avizienis
c42d8149b7
moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
2011-11-17 23:50:45 -08:00
Rimas Avizienis
5a322ff00c
fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions
2011-11-17 11:17:37 -08:00
Rimas Avizienis
80b4253318
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
2011-11-16 02:04:28 -08:00
Rimas Avizienis
886857fa47
writes of PC weren't being sign extended
2011-11-15 18:07:36 -08:00
Rimas Avizienis
fc0f20643a
cleanup
2011-11-15 18:06:41 -08:00
Rimas Avizienis
ae98956e6b
more amo fixes, added more options to testharness to control debug messages
2011-11-15 02:43:51 -08:00
Rimas Avizienis
82a636ff55
AMOADD, AMOAND, AMOOR, AMOSWAP working
2011-11-15 00:51:45 -08:00
Rimas Avizienis
48cec01710
updated riscv-bmarks and riscv-tests to build with new toolchain
2011-11-15 00:11:22 -08:00
Rimas Avizienis
db87924fbf
made eret instruction take an illegal inst exception when ET is set
2011-11-14 14:35:10 -08:00
Rimas Avizienis
cd6e463320
added ei and di instructions
2011-11-14 13:48:49 -08:00
Rimas Avizienis
b791010bb1
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
2011-11-14 04:13:13 -08:00
Rimas Avizienis
890bfa7c48
added IPIs and timer interrupts
2011-11-14 03:24:02 -08:00
Rimas Avizienis
5b29765917
synced up with supervisor mode state in latest ISA simulator
2011-11-14 01:37:20 -08:00
Rimas Avizienis
9d3471a569
more cache fixes, more test harness debug output
2011-11-13 23:32:18 -08:00
Rimas Avizienis
67c7e7e28f
cache/tlb bugfixes, increased memory size to 256meg
2011-11-13 13:06:35 -08:00
Rimas Avizienis
29d44b8bc5
fixed typo that broke illegal instruction exception
2011-11-13 01:17:33 -08:00
Rimas Avizienis
7b3c34a341
regenerated instruction encodings using parse-opcodes
2011-11-13 00:59:02 -08:00
Rimas Avizienis
44419511b7
timer interrupt fixes
2011-11-13 00:32:08 -08:00
Rimas Avizienis
345f950eff
added timer interrupt support
2011-11-13 00:27:57 -08:00
Rimas Avizienis
5f4b15b809
added ld/st misaligned exceptions
2011-11-13 00:03:17 -08:00
Rimas Avizienis
fbd44ea936
added checks for addresses > physical memory size, increased memsize to 64M
2011-11-12 23:39:43 -08:00
Rimas Avizienis
35af912bd2
cache optimizations, cleanup, and testharness improvement
2011-11-12 22:13:29 -08:00
Rimas Avizienis
91c252ad08
fixing output enable signals for data/tag SRAMs
2011-11-12 15:47:47 -08:00
Rimas Avizienis
83d90c4dab
more itlb/dtlb/ptw fixes
2011-11-12 15:00:45 -08:00
Rimas Avizienis
73416f224b
more tlb/ptw debugging
2011-11-12 00:25:06 -08:00
Rimas Avizienis
44926866b7
updated itlb
2011-11-11 18:48:34 -08:00
Rimas Avizienis
a1ce908541
dcache/dtlb overhaul
2011-11-11 18:18:47 -08:00
Rimas Avizienis
e4fa94aa27
checkpoint
2011-11-10 17:41:22 -08:00
Rimas Avizienis
f86d5b1334
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
2011-11-10 11:26:13 -08:00
Rimas Avizienis
4bd0263a4a
added misaligned instruction check, cleaned up badvaddr handling
2011-11-10 03:38:59 -08:00
Rimas Avizienis
603ede8bfe
access faults now write badvaddr PCR register with faulting address
2011-11-10 02:46:09 -08:00
Rimas Avizienis
36aa4bcc9d
moved exception handling from ex stage in dpath to mem stage in ctrl
2011-11-10 02:26:26 -08:00
Rimas Avizienis
fbfa356d2a
fixed eret instruction
2011-11-10 00:37:00 -08:00
Rimas Avizienis
62407b4668
more tlb/ptw fixes
2011-11-10 00:23:29 -08:00
Rimas Avizienis
6664af3bc0
cleanup before adding dtlb
2011-11-09 23:27:29 -08:00
Rimas Avizienis
9aca403aa8
more itlb integration & cleanup
2011-11-09 23:18:14 -08:00
Rimas Avizienis
c29d2821b4
cleanup, fixes, initial commit for dtlb.scala
2011-11-09 21:54:11 -08:00
Rimas Avizienis
e96430d862
integrating ITLB & PTW
2011-11-09 14:52:17 -08:00
Rimas Avizienis
7130edac8d
fix for flushed div/mul instructions
2011-11-07 01:03:47 -08:00
Rimas Avizienis
9d63087eb2
changed caches to use separate sram modules for tag and data arrays
2011-11-07 00:58:25 -08:00
Rimas Avizienis
4d64099103
cleanup
2011-11-04 20:52:21 -07:00
Rimas Avizienis
2db9ee12bc
fixed eret instruction, hello world runs
2011-11-04 15:57:08 -07:00
Rimas Avizienis
4459935554
dcache fixes - all tests and ubmarks pass, hello world still broken
2011-11-04 15:40:41 -07:00
Rimas Avizienis
3a02028a35
fixes to exception and dcache miss/blocked handling
2011-11-02 13:32:32 -07:00
Rimas Avizienis
7a528d6255
fixes for div/mul hazard checking + cleanup
2011-11-01 23:14:34 -07:00
Rimas Avizienis
d8ffecf565
dcache fix
2011-11-01 22:10:06 -07:00
Rimas Avizienis
7479e085ec
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 22:04:45 -07:00
Rimas Avizienis
3b3d988fde
dcache loads working - 1/2 cycle load/use delay depending on load type
2011-11-01 21:25:52 -07:00
Rimas Avizienis
2b67eee683
pipeline changes for replay on dcache miss
2011-11-01 19:05:27 -07:00
Rimas Avizienis
08b89e7710
interface cleanup, major pipeline changes
2011-11-01 17:59:27 -07:00
Rimas Avizienis
ace4c9d13c
dcache fixes
2011-10-31 17:17:36 -07:00
Rimas Avizienis
65f8b2461c
dcache tweaks
2011-10-31 16:47:31 -07:00
Rimas Avizienis
172e561a78
added once cycle latency store pipelined d$
2011-10-31 15:37:37 -07:00
Rimas Avizienis
c06e2d16e4
initial commit of rocket chisel project, riscv assembly tests and benchmarks
2011-10-25 23:02:47 -07:00
