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Commit Graph

71 Commits

Author SHA1 Message Date
Andrew Waterman
bc15e8649e WIP on priv spec v1.9 2016-03-02 23:29:58 -08:00
Howard Mao
120361226d fix more Chisel3 deprecations 2016-01-14 14:46:31 -08:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Henry Cook
84576650b5 Removed all traces of params 2015-10-05 21:48:05 -07:00
Andrew Waterman
833909a2b5 Chisel3 compatibility fixes 2015-09-30 14:36:26 -07:00
Andrew Waterman
78b2e947de Chisel3 compatibility fixes 2015-09-11 15:43:07 -07:00
Andrew Waterman
546205b174 Chisel3 compatibility: use >>Int instead of >>UInt 2015-08-05 15:29:03 -07:00
Andrew Waterman
57930e8a26 Chisel3 compatibility potpourri 2015-07-30 23:53:02 -07:00
Andrew Waterman
ce161b83e3 Chisel3 compatibility: avoid subword assignment 2015-07-29 15:03:13 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
f460cb6c54 Update to privileged architecture 1.7 2015-05-19 02:32:21 -07:00
Andrew Waterman
bce62d5774 Update PTE format to reflect reserved bits 2015-04-04 15:19:15 -07:00
Andrew Waterman
d912ea265e New virtual memory implementation (Sv39) 2015-03-27 16:20:59 -07:00
Andrew Waterman
0332c1e7fe Reduce latency of page table walks
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
2015-03-24 18:58:38 -07:00
Andrew Waterman
e85c54cc4b New privileged ISA implementation 2015-03-14 02:49:07 -07:00
Christopher Celio
06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache 2015-03-03 16:50:41 -08:00
Henry Cook
741e6b77ad Rename some params, use refactored TileLink 2015-02-01 20:37:31 -08:00
Yunsup Lee
8abf62fae3 add LICENSE 2014-09-12 18:06:41 -07:00
Henry Cook
2de268b3b1 Cache utility traits. Completely compiles, asm tests hang. 2014-08-19 11:38:20 -07:00
Henry Cook
0dac9a7467 Full conversion to params. Compiles but does not elaborate. 2014-08-19 11:38:02 -07:00
Andrew Waterman
4ca152b012 Use BundleWithConf to avoid clone method boilerplate 2014-05-09 19:37:16 -07:00
Henry Cook
1fa505f9ff remove superfluous AVec object 2014-04-16 17:19:32 -07:00
Henry Cook
910b3b203a removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants 2014-04-10 12:32:44 -07:00
Andrew Waterman
e8486817e6 Clean up formatting (i.e. remove tabs, semicolons) 2014-01-13 21:43:56 -08:00
Andrew Waterman
924261e2b2 Update to new privileged ISA... phew 2013-11-25 04:35:15 -08:00
Henry Cook
d06e24ac24 new enum syntax 2013-09-10 10:51:35 -07:00
Andrew Waterman
d4a0db4575 Reflect ISA changes 2013-08-24 14:43:55 -07:00
Henry Cook
3a266cbbfa final Reg changes 2013-08-15 15:28:15 -07:00
Henry Cook
1a9e43aa11 initial attempt at upgrade 2013-08-12 10:39:11 -07:00
Henry Cook
9abdf4e154 Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object. 2013-07-23 20:27:58 -07:00
Andrew Waterman
8cbdeb2abf add LR/SC support 2013-04-04 17:07:09 -07:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
90cae54ac4 fix D$ read/write concurrency bug 2012-11-27 02:42:27 -08:00
Andrew Waterman
9c857b83f0 refactor PCR file 2012-11-27 01:28:06 -08:00
Andrew Waterman
64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS 2012-11-26 20:38:45 -08:00
Andrew Waterman
8dce89703a new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
Andrew Waterman
e76892f758 remove more global constants 2012-11-06 02:55:45 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Andrew Waterman
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Henry Cook
5d2a470215 all rocket-specific arbiters in one file and refactored traits slightly 2012-10-15 16:05:32 -07:00
Henry Cook
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Andrew Waterman
e1f9dc2c1f generalize page table walker
also, don't instantiate vitlb when !HAVE_VEC
2012-05-03 02:29:09 -07:00
Henry Cook
622a801bb1 Refactored cpu/cache interface to use nested bundles 2012-05-02 11:54:28 -07:00
Andrew Waterman
eafdffe125 simplify page table walker; speed up emulator 2012-05-01 01:24:36 -07:00
Yunsup Lee
62ada5ea9e hookup vitlb ptw port 2012-03-17 23:01:06 -07:00
Andrew Waterman
6c26921766 reduce D$ critical path through page table walker
costs an extra cycle per page table level to resolve a TLB miss. too bad.
2012-03-16 18:35:54 -07:00