125 lines
3.4 KiB
Scala
125 lines
3.4 KiB
Scala
package rocket
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import Chisel._
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import uncore._
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import Util._
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class PTWResp extends Bundle {
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val error = Bool()
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val ppn = UInt(width = params(PPNBits))
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val perm = Bits(width = params(PermBits))
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}
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class TLBPTWIO extends Bundle {
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val req = Decoupled(UInt(width = params(VPNBits)))
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val resp = Valid(new PTWResp).flip
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val status = new Status().asInput
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val invalidate = Bool(INPUT)
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val sret = Bool(INPUT)
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}
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class DatapathPTWIO extends Bundle {
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val ptbr = UInt(INPUT, params(PAddrBits))
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val invalidate = Bool(INPUT)
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val sret = Bool(INPUT)
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val status = new Status().asInput
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}
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class PTW(n: Int) extends Module
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{
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val io = new Bundle {
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val requestor = Vec.fill(n){new TLBPTWIO}.flip
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val mem = new HellaCacheIO
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val dpath = new DatapathPTWIO
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}
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val levels = 3
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val bitsPerLevel = params(VPNBits)/levels
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require(params(VPNBits) == levels * bitsPerLevel)
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val s_ready :: s_req :: s_wait :: s_done :: s_error :: Nil = Enum(UInt(), 5)
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val state = Reg(init=s_ready)
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val count = Reg(UInt(width = log2Up(levels)))
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val r_req_vpn = Reg(Bits())
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val r_req_dest = Reg(Bits())
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val r_pte = Reg(Bits())
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val vpn_idx = Vec((0 until levels).map(i => (r_req_vpn >> (levels-i-1)*bitsPerLevel)(bitsPerLevel-1,0)))(count)
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val arb = Module(new RRArbiter(UInt(width = params(VPNBits)), n))
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arb.io.in <> io.requestor.map(_.req)
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arb.io.out.ready := state === s_ready
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when (arb.io.out.fire()) {
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r_req_vpn := arb.io.out.bits
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r_req_dest := arb.io.chosen
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r_pte := Cat(io.dpath.ptbr(params(PAddrBits)-1,params(PgIdxBits)), io.mem.resp.bits.data(params(PgIdxBits)-1,0))
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}
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when (io.mem.resp.valid) {
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r_pte := io.mem.resp.bits.data
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}
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io.mem.req.valid := state === s_req
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io.mem.req.bits.phys := Bool(true)
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io.mem.req.bits.cmd := M_XRD
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io.mem.req.bits.typ := MT_D
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io.mem.req.bits.addr := Cat(r_pte(params(PAddrBits)-1,params(PgIdxBits)), vpn_idx).toUInt << log2Up(params(XprLen)/8)
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io.mem.req.bits.kill := Bool(false)
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val resp_val = state === s_done || state === s_error
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val resp_err = state === s_error || state === s_wait
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val r_resp_ppn = io.mem.req.bits.addr >> UInt(params(PgIdxBits))
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val resp_ppn = Vec((0 until levels-1).map(i => Cat(r_resp_ppn >> bitsPerLevel*(levels-i-1), r_req_vpn(bitsPerLevel*(levels-i-1)-1,0))) :+ r_resp_ppn)(count)
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for (i <- 0 until io.requestor.size) {
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val me = r_req_dest === UInt(i)
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io.requestor(i).resp.valid := resp_val && me
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io.requestor(i).resp.bits.error := resp_err
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io.requestor(i).resp.bits.perm := r_pte(8,3)
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io.requestor(i).resp.bits.ppn := resp_ppn.toUInt
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io.requestor(i).invalidate := io.dpath.invalidate
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io.requestor(i).sret := io.dpath.sret
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io.requestor(i).status := io.dpath.status
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}
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// control state machine
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switch (state) {
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is (s_ready) {
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when (arb.io.out.valid) {
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state := s_req
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}
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count := UInt(0)
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}
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is (s_req) {
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when (io.mem.req.ready) {
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state := s_wait
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}
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}
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is (s_wait) {
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when (io.mem.resp.bits.nack) {
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state := s_req
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}
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when (io.mem.resp.valid) {
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state := s_error
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when (io.mem.resp.bits.data(0)) {
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when (!io.mem.resp.bits.data(1)) {
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state := s_done
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}.elsewhen (count < levels-1) {
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state := s_req
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count := count + 1
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}
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}
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}
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}
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is (s_done) {
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state := s_ready
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}
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is (s_error) {
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state := s_ready
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}
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}
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}
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