Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
|
Henry Cook
|
12caa55dc7
|
wip: new network classes
|
2012-12-06 18:51:30 -08:00 |
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
10a6a42a4a
|
make vlsi use dram model by default
|
2012-12-06 03:13:45 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|
Andrew Waterman
|
290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
Andrew Waterman
|
aae7a67781
|
fix llc refill/writeback bugs
|
2012-12-06 02:07:03 -08:00 |
|
Andrew Waterman
|
d911e635d6
|
simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
|
2012-12-04 07:04:26 -08:00 |
|
Andrew Waterman
|
50e9d952e8
|
don't initiate llc refill until writeback drains
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2012-12-04 06:57:53 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
5dfb388f03
|
update to newest rocket
|
2012-11-27 02:43:31 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
ea7029484e
|
update to latest rocket
|
2012-11-26 20:57:12 -08:00 |
|
Andrew Waterman
|
8103676b37
|
reduce physical address space to 4GB
|
2012-11-26 20:54:56 -08:00 |
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
|
2012-11-26 20:34:30 -08:00 |
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
|
2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
|
e12af07722
|
update to newest rocket
|
2012-11-25 04:40:46 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
b514c7b725
|
clean up I$ parity code
|
2012-11-24 22:00:43 -08:00 |
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
|
9372912a9c
|
update to newest rocket
|
2012-11-20 05:42:44 -08:00 |
|
Andrew Waterman
|
6d47d18c2b
|
catch sigterm to gracefully exit (fixes vcd)
|
2012-11-20 05:40:44 -08:00 |
|
Andrew Waterman
|
7330deb13a
|
print stack trace if elaboration fails
|
2012-11-20 05:39:48 -08:00 |
|
Andrew Waterman
|
56f9b9721d
|
treat prefetches as read requests
|
2012-11-20 05:38:49 -08:00 |
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
4d73e6e38a
|
revamp vector yet again with new D$
|
2012-11-18 03:14:22 -08:00 |
|
Yunsup Lee
|
6bd4f93f8c
|
pull out prefetch commands from isRead
|
2012-11-18 03:13:17 -08:00 |
|
Yunsup Lee
|
395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
|
2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
06eeb90e2a
|
vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
7bcf59a18f
|
support continous compilation via "make test"
for c++ emulator only, for now
|
2012-11-17 19:58:18 -08:00 |
|
Andrew Waterman
|
b58214d7e3
|
remove more global constants
|
2012-11-17 17:25:43 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
cf05b604b3
|
upgrade to new rocket; improve vlsi makefiles
|
2012-11-17 07:21:29 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
|
672e904c86
|
update to new rocket/uncore
|
2012-11-16 02:41:50 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
3e6dc35809
|
issue self-probes for uncached read transactions
this facilitates I$ coherence. but it seems like a hack and perhaps
the mechanism should be rethought.
|
2012-11-16 02:37:56 -08:00 |
|
Andrew Waterman
|
a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|