Schuyler Eldridge
cfd49f87c1
Use longname for ElaborationArtefact emission
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 16:55:13 -05:00
Schuyler Eldridge
e52d52ae99
Link PlusArg to emulator command line options
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- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
Megan Wachs
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
Henry Cook
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
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Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
pentin-as
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
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In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
Henry Cook
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
Henry Cook
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
Henry Cook
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
Albert Huntington
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
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Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
Megan Wachs
a530646d15
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-08 09:11:27 -08:00
Henry Cook
4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port
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Fix TL MMIO port
2018-01-05 20:37:44 -08:00
Megan Wachs
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
Albert Huntington
8425086f98
Allow rwReg to pass name and description to RegField for documentation.
2018-01-05 16:59:58 -08:00
Megan Wachs
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
Megan Wachs
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
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This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
Henry Cook
b77b93b0b4
util: dontTouchPortsExcept
2018-01-05 14:06:00 -08:00
Andrew Waterman
000cde2f8a
Make ErrorDevice UNCACHEABLE instead of UNCACHED
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...even though it still supports Acquire. This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00
Andrew Waterman
ad0b9a0b1b
Reduce cases in which FENCE.I must flush D$
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Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
Henry Cook
4853d1355f
rocket: dontTouch HellaCache.io.cpu.resp
2018-01-05 12:50:24 -08:00
Henry Cook
847efde385
coreplex: dontTouch the tile_inputs wire
2018-01-05 12:47:41 -08:00
Wesley W. Terpstra
f749e986cf
coreplex: fix TL MMIO port example
2018-01-05 12:29:47 +01:00
Andrew Waterman
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
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Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
Andrew Waterman
ee1a9485df
Enforce physical-address canonicalization
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When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
Andrew Waterman
7c9a1b0265
Correctly check for virtual-address canonicalization
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The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
Henry Cook
320900f76c
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
Henry Cook
b0e1bc3071
tile: cake reduction
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* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
Henry Cook
efe7165b54
tile: BaseTile refactor, pt 2
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* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
Henry Cook
1579ddb97e
tile: removed RocketTileWrapper. RocketTile now HasCrossing.
2017-12-28 14:00:13 -08:00
Henry Cook
1cd018546c
tile: BaseTile refactor, pt 1
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* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00
Henry Cook
ba6dd160a3
diplomacy: allow access to sram Device info
2017-12-22 19:00:43 -08:00
Henry Cook
d9c5ec4f7b
coreplex: HasTiles supplies def tileParams
2017-12-20 17:18:55 -08:00
Henry Cook
ddaeedf2d0
coreplex: make HasTiles more generic
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HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
2017-12-20 17:18:55 -08:00
Henry Cook
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )" ( #1162 )
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This reverts commit a542ae687e
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2017-12-19 12:16:26 -08:00
Megan Wachs
74d9326ebc
JTAG: Revert to Chisel._ for Issue 1160 ( #1161 )
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* JTAG: Revert to Chisel._ for Issue 1160
* JTAG: Revert to Chisel._ for Issue 1160
* jtag: revert everything to Chisel._
* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
2017-12-18 21:02:31 -08:00
Henry Cook
a31ba2ea2e
diplomacy: LazyModule factory uses ValName ( #1159 )
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* diplomacy: LazyModule factory uses ValName
2017-12-18 15:40:30 -08:00
Jacob Chang
09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… ( #1155 )
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* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there
* rocket: add d-channel error to I$
2017-12-13 20:16:36 -08:00
Wesley W. Terpstra
a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) ( #1144 )
2017-12-08 17:35:14 -08:00
Wesley W. Terpstra
c2a0319dc4
Merge pull request #1151 from freechipsproject/error-atoms
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Error atomics
2017-12-08 17:34:55 -08:00
Wesley W. Terpstra
efc793d52e
CloneModule: must be public to be used in pattern matches
2017-12-08 14:57:08 -08:00
Wesley W. Terpstra
2ca03384ec
diplomacy: skip anonymous class names
2017-12-08 14:36:12 -08:00
Jack Koenig
588dacec17
Bump Chisel and Firrtl ( #1134 )
2017-12-08 14:22:18 -08:00
Wesley W. Terpstra
18b8a61775
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
Wesley W. Terpstra
6a0150aad7
Error device: mark executable to support testing erroneous I$ refill
2017-12-08 12:38:06 -08:00
Andrew Waterman
676110bc1f
Add cover for a1ebe6da4d
2017-12-07 21:03:42 -08:00
Andrew Waterman
a1ebe6da4d
Prevent frontend deadlock fetching from uncacheable memory
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After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch. This prevents the frontend from replaying
forever.
2017-12-07 18:56:06 -08:00
Jacob Chang
ec3789b365
Add Cross Cover Property Library ( #1149 )
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Add cover points related to memory error to I/D Cache
2017-12-07 18:46:10 -08:00
Andrew Waterman
5c204f98d5
When writing full words to ITIM, ECC errors are correctable ( #1148 )
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* When writing full words to ITIM, ECC errors are correctable
* Disable D$ tag reset state machine when using scratchpad
2017-12-07 16:00:26 -08:00
Richard Xia
50de991f18
Fix typo in breakpoint cover property.
2017-12-04 14:04:24 -08:00
Wesley W. Terpstra
b8098d18be
diplomacy: remove the :=? operator in favour of magic :*=* ( #1139 )
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The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.
Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.
The new :*=* just automagically figures it out from the graph.
2017-12-01 18:28:37 -08:00
Wesley W. Terpstra
dedf396915
groundtest: connect the ibus to a fictitious master ( #1140 )
2017-12-01 18:28:24 -08:00