Schuyler Eldridge
cfd49f87c1
Use longname for ElaborationArtefact emission
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 16:55:13 -05:00
Schuyler Eldridge
e52d52ae99
Link PlusArg to emulator command line options
...
- adds a mutable singleton (PlusArgArtefacts) to store information
about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
consumed by emulator.cc for correct argument parsing and help text
generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-15 14:32:55 -05:00
Megan Wachs
8799508b1f
Merge pull request #1179 from freechipsproject/refactored_rbb
...
Add Debug tests to Regressions
2018-01-12 10:34:48 -08:00
Jordan Danford
b8219425d8
Fix spelling and capitalization in README.md
( #1182 )
2018-01-10 15:52:07 -08:00
Megan Wachs
5fe0bb0d6a
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-09 21:34:14 -08:00
Henry Cook
f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2
...
Make more use of chisel3.experimental.DontTouch
2018-01-09 15:13:55 -08:00
pentin-as
c152962642
Dual-port RAM replaced with single-port RAM for tag_array in HellaCache ( #1181 )
...
In accordance with https://github.com/freechipsproject/chisel3/issues/752
2018-01-09 13:06:43 -08:00
Henry Cook
15c54b1c5a
tile: intSinkNode belongs in HasExternalInterrupts
2018-01-08 19:38:10 -08:00
Henry Cook
11e5b620f8
tile: disable more monitors on slave port
2018-01-08 18:42:25 -08:00
Henry Cook
5075a93e6c
util: dontTouch work-around for zero width aggregates
2018-01-08 15:58:28 -08:00
Albert Huntington
7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc
...
Allow rwReg to pass name and description to RegField for documentation.
2018-01-08 09:44:44 -08:00
Megan Wachs
a530646d15
Merge remote-tracking branch 'origin/master' into refactored_rbb
2018-01-08 09:11:27 -08:00
Henry Cook
4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port
...
Fix TL MMIO port
2018-01-05 20:37:44 -08:00
Henry Cook
3525489fff
Merge pull request #1174 from freechipsproject/error-device-tracked
...
Claim that ErrorDevice is TRACKED
2018-01-05 17:17:22 -08:00
Megan Wachs
427b6c9ab8
Emulator: Update it to allow some hard-coded Verilog PlusArgs
2018-01-05 17:08:21 -08:00
Megan Wachs
76c5fd0c0c
travis: Use newer infrastructure, but require sudo for additional disk space.
...
This is because as of Dec 12, 2017, Travis changed their container images and seem
to give slightly less disk space. Using a sudo image gives more disk space.
2018-01-05 17:08:21 -08:00
Megan Wachs
e6661a6982
Debug regressions: use a plusarg to enable remote bitbang.
2018-01-05 17:08:21 -08:00
Megan Wachs
b643f3dca6
debug regressions: some whitespace and null ptr cleanup
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
96dd5d8c38
Emulator example clarifications
...
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
7ae6bf7611
Arguments clarification, add examples
...
This clarifies and provides consistent for the command line arguments
usage text.
This adds a set of examples for running the rocket-chip emulator.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
1aa87f6578
Make emulator.cc understand HTIF arguments
...
This, with riscv-fesvr modifications, enables the rocket-chip emulator
to understand (and error out) if a command line argument that will
eventually be consumed by HTIF looks bad and can error out quickly.
This relies on modifications to risc-fesvr to support getopt and the
exposure of what HTIF arguments exist via the `htif.h` header.
2018-01-05 17:08:21 -08:00
Schuyler Eldridge
3ead9a5d2d
Move check on VCS inside riscv-fesvr
...
This removes the necessary preprocessing of riscv-fesvr arguments to
avoid situations where riscv-fesvr thinks that an argument is the
binary. Support for this is rolled into riscv-fesvr.
2018-01-05 17:08:21 -08:00
Megan Wachs
a97add954a
Async Reg: Doesn't properly reset for Verilator.
2018-01-05 17:08:21 -08:00
Megan Wachs
9df3604007
emulator: No reason not to emit waveforms during reset
2018-01-05 17:08:21 -08:00
Megan Wachs
024cd52c44
debug: attempt to make the simulation deterministic by not returning until connection is made and command is receieved
2018-01-05 17:08:21 -08:00
Megan Wachs
1d3fa07c44
debug: print failures when debug tests fail, so we can see why it is failing on Travis
...
Cleanups, and print out log names ASAP.
Factor out gdbserver common invocation into GDBSERVER (fixing
--print-failtures).
Add --print-log-names to that command so the logfiles can be inspected
while the simulation is still running.
`RISCV=... cmd` is more idiomatic than `export RISCV=... && cmd`
2018-01-05 17:08:15 -08:00
Albert Huntington
8425086f98
Allow rwReg to pass name and description to RegField for documentation.
2018-01-05 16:59:58 -08:00
Megan Wachs
9b234216f0
debug: Install pexpect package for travis regressions
2018-01-05 16:13:19 -08:00
Megan Wachs
1549ecfb3f
debug: explicitly clone riscv-tests to get to gdbserver.py
2018-01-05 16:13:11 -08:00
Megan Wachs
3de9a04272
debug regression: until XLEN fix is merged into riscv-tests, have to explicitly state the XLEN
2018-01-05 16:10:13 -08:00
Megan Wachs
bd5fe5d22e
Debug regression: have to say something about memory in order to run a simple test
2018-01-05 16:10:13 -08:00
Megan Wachs
5df55d7911
debug regression: bump riscv-tools for riscv-tests fixes
2018-01-05 16:10:13 -08:00
Megan Wachs
593839e0d5
Debug: add Debug regression to Travis regressions.
2018-01-05 16:10:00 -08:00
Megan Wachs
4449dd0baa
Debug regressions: Add necessary config scripts
2018-01-05 16:03:59 -08:00
Megan Wachs
e82328336e
Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface.
...
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
2018-01-05 16:02:52 -08:00
Henry Cook
b77b93b0b4
util: dontTouchPortsExcept
2018-01-05 14:06:00 -08:00
Andrew Waterman
000cde2f8a
Make ErrorDevice UNCACHEABLE instead of UNCACHED
...
...even though it still supports Acquire. This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
2018-01-05 14:00:42 -08:00
Andrew Waterman
ad0b9a0b1b
Reduce cases in which FENCE.I must flush D$
...
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
2018-01-05 13:58:14 -08:00
Henry Cook
4853d1355f
rocket: dontTouch HellaCache.io.cpu.resp
2018-01-05 12:50:24 -08:00
Henry Cook
847efde385
coreplex: dontTouch the tile_inputs wire
2018-01-05 12:47:41 -08:00
Wesley W. Terpstra
f749e986cf
coreplex: fix TL MMIO port example
2018-01-05 12:29:47 +01:00
Andrew Waterman
206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check
...
Enforce physical-address canonicalization
2018-01-03 12:06:18 -08:00
Henry Cook
1bd343bcef
Merge pull request #1156 from freechipsproject/has-tiles
...
coreplex: make HasTiles more generic
2018-01-02 19:38:17 -08:00
Andrew Waterman
ee1a9485df
Enforce physical-address canonicalization
...
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
2018-01-02 18:47:30 -08:00
Andrew Waterman
7c9a1b0265
Correctly check for virtual-address canonicalization
...
The previous check was necessary but not sufficient.
2018-01-02 18:41:25 -08:00
Henry Cook
320900f76c
tile: BaseTileModule => BaseTileModuleImp
2018-01-02 17:55:54 -08:00
Henry Cook
b0e1bc3071
tile: cake reduction
...
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
2018-01-02 17:49:08 -08:00
Henry Cook
efe7165b54
tile: BaseTile refactor, pt 2
...
* 2 layer cake
* no more bundle traits, only call to IO
2018-01-02 15:37:31 -08:00
Henry Cook
1579ddb97e
tile: removed RocketTileWrapper. RocketTile now HasCrossing.
2017-12-28 14:00:13 -08:00
Henry Cook
1cd018546c
tile: BaseTile refactor, pt 1
...
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
2017-12-26 11:04:15 -08:00