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rocket-chip
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rocket-chip
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src
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main
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scala
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Henry Cook
895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (
#1144
)" (
#1162
)
...
This reverts commit a542ae687e6bd2e459939aee7fd98dddb399bed1.
2017-12-19 12:16:26 -08:00
..
amba
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
config
config: fix warning
2017-09-22 14:58:36 -07:00
coreplex
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
devices
Error device: require explicit control of atomic and transfer sizes
2017-12-08 13:41:09 -08:00
diplomacy
diplomacy: LazyModule factory uses ValName (
#1159
)
2017-12-18 15:40:30 -08:00
groundtest
groundtest: connect the ibus to a fictitious master (
#1140
)
2017-12-01 18:28:24 -08:00
interrupts
diplomacy: provide a val name for all LazyModule constructions
2017-12-01 11:28:21 -08:00
jtag
JTAG: Revert to Chisel._ for Issue 1160 (
#1161
)
2017-12-18 21:02:31 -08:00
regmapper
regmapper: fix d_ready => d_bits loop in RegField.bytes
2017-11-30 16:38:45 -08:00
rocket
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (
#1144
)" (
#1162
)
2017-12-19 12:16:26 -08:00
system
coreplex: WithStatelessBridge => WithIncoherentTiles (
#1092
)
2017-11-07 13:47:56 -08:00
tile
DTS: collect common DTS nodes and move timebase-frequency to cores
2017-11-20 18:09:57 -08:00
tilelink
diplomacy: remove the :=? operator in favour of magic :*=* (
#1139
)
2017-12-01 18:28:37 -08:00
unittest
unittest: add an API for describing LazyModule unit tests
2017-12-01 11:26:59 -08:00
util
Add Cross Cover Property Library (
#1149
)
2017-12-07 18:46:10 -08:00