Andrew Waterman
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d04da83f96
|
Make data RAMs 1RW instead of 1R1W
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2014-12-15 17:36:17 -08:00 |
|
Henry Cook
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6a8b66231c
|
Add uncached->cached tilelink converter
|
2014-12-12 17:06:03 -08:00 |
|
Henry Cook
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424df2368f
|
1R/W L2 data array?
Add TLDataBeats to new LLC; all bmarks pass
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2014-12-12 17:05:21 -08:00 |
|
Henry Cook
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3026c46a9c
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Finish adding TLDataBeats to uncore & hub
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2014-12-12 17:04:52 -08:00 |
|
Henry Cook
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2f733a60db
|
Begin adding TLDataBeats to uncore
|
2014-12-12 17:04:31 -08:00 |
|
Henry Cook
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404773eb9f
|
fix wb bug
|
2014-12-03 14:22:39 -08:00 |
|
Henry Cook
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05b5188ad9
|
meta and data bundle refactor
|
2014-11-19 15:55:25 -08:00 |
|
Henry Cook
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a519a43f23
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Merge branch 'master' into new-llc
Conflicts:
src/main/scala/coherence.scala
src/main/scala/memserdes.scala
src/main/scala/tilelink.scala
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2014-11-12 16:25:25 -08:00 |
|
Henry Cook
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cb7e712599
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Added uncached write data queue to coherence hub
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2014-11-12 12:55:07 -08:00 |
|
Henry Cook
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82155f333e
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Major tilelink revision for uncached message types
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2014-11-11 17:36:55 -08:00 |
|
Henry Cook
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35553cc0b7
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NullDirectory sharers.count fix
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2014-11-11 16:05:25 -08:00 |
|
Henry Cook
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10309849b7
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Remove master_xact_id from Probe and Release
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2014-11-06 12:07:33 -08:00 |
|
Henry Cook
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27c72e5eed
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nearly all isa tests pass
|
2014-10-23 21:50:03 -07:00 |
|
Henry Cook
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a891ba1d46
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more correct handling of internal state
|
2014-10-21 17:40:30 -07:00 |
|
Yunsup Lee
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170f1fecbc
|
push chisel,rocket,riscv-tools
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2014-10-21 12:32:58 -07:00 |
|
Henry Cook
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044b19dbc1
|
Compiles and elaborates, does not pass asm tests
|
2014-10-15 11:46:35 -07:00 |
|
Henry Cook
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86bdbd6535
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new tshrs, compiles but does not elaborate
|
2014-10-07 22:33:10 -07:00 |
|
Yunsup Lee
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1b31931981
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Merge pull request #2 from wasserfuhr/patch-1
Update README.md
|
2014-10-07 17:02:55 -07:00 |
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RainerWasserfuhr
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9b41ad92ba
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Update README.md
typo?
|
2014-10-08 01:46:48 +02:00 |
|
Yunsup Lee
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f15baeea49
|
fix markdown for webpage
|
2014-10-07 03:55:00 -07:00 |
|
Yunsup Lee
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5ca7f08226
|
change rocket submodule
|
2014-10-07 03:19:48 -07:00 |
|
Yunsup Lee
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e1b8f69cb5
|
change submodule pointers to https
|
2014-10-07 03:16:20 -07:00 |
|
Yunsup Lee
|
447761b06c
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fix typo in README
|
2014-10-07 02:09:34 -07:00 |
|
Yunsup Lee
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91f211f766
|
updates to README
|
2014-10-07 02:08:03 -07:00 |
|
Yunsup Lee
|
702ddabe26
|
add ExampleSmallConfig for README
|
2014-10-07 02:07:59 -07:00 |
|
Yunsup Lee
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ae9b78d9ef
|
add what/how explanation to README
|
2014-10-07 02:07:39 -07:00 |
|
Scott Beamer
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5f55ded723
|
bump fpga submodule
|
2014-10-06 13:45:12 -07:00 |
|
Scott Beamer
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06bc6a45db
|
move fpga repo to git@ from https
|
2014-10-06 13:45:09 -07:00 |
|
Henry Cook
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23ae6893ad
|
bump chisel
|
2014-10-06 13:45:03 -07:00 |
|
Yunsup Lee
|
e25d420155
|
Improve ChiselConfig composability; bump chisel
|
2014-10-06 13:43:40 -07:00 |
|
Yunsup Lee
|
73eac94a65
|
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
|
2014-10-06 13:40:35 -07:00 |
|
Henry Cook
|
f97a801d60
|
Parameter API update
|
2014-10-06 13:37:42 -07:00 |
|
Henry Cook
|
122733b3a9
|
file name consistency
|
2014-10-06 13:37:38 -07:00 |
|
Henry Cook
|
a9d72aac2a
|
bump rocket
|
2014-10-06 13:37:27 -07:00 |
|
Henry Cook
|
0b5f23a209
|
Streamlined uncore for release
|
2014-10-06 13:37:15 -07:00 |
|
Henry Cook
|
394eb38a96
|
temp; converted voluntary wb tracker
|
2014-10-03 01:06:49 -07:00 |
|
Henry Cook
|
dc1a61264d
|
initial version, acts like old hub
|
2014-10-03 01:06:49 -07:00 |
|
Henry Cook
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d735f64110
|
Parameter API update
|
2014-10-02 16:47:35 -07:00 |
|
Yunsup Lee
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6c18cd9559
|
add new fpga-zynq as submodule
|
2014-09-30 09:32:02 -07:00 |
|
Yunsup Lee
|
7a28d2b47c
|
forgot to move more hwacha stuff out in rocket-chip
|
2014-09-25 15:34:18 -07:00 |
|
Yunsup Lee
|
70b0f9fd4d
|
error out for PCWM-L, port width mismatch
|
2014-09-25 06:50:50 -07:00 |
|
Adam Izraelevitz
|
15fb4730ec
|
Add BuildTile parameter for Tile
Conflicts:
rocket
|
2014-09-25 06:50:45 -07:00 |
|
Henry Cook
|
7398b00d93
|
dir supplied by function
|
2014-09-25 06:50:41 -07:00 |
|
Henry Cook
|
db4de7b806
|
bump chisel
|
2014-09-25 06:50:36 -07:00 |
|
Henry Cook
|
5a840c5520
|
support for multiple tilelink paramerterizations in same design
|
2014-09-25 06:50:30 -07:00 |
|
Yunsup Lee
|
e2ed81dcd2
|
push chisel
|
2014-09-25 06:50:05 -07:00 |
|
Donggyu Kim
|
eb384f6461
|
new RocketChipBackend implementation
|
2014-09-25 06:47:12 -07:00 |
|
Scott Beamer
|
f2ca887de3
|
better fpga configs
|
2014-09-25 06:47:03 -07:00 |
|
Donggyu Kim
|
4fe48f5a0a
|
bump chisel
|
2014-09-25 06:46:58 -07:00 |
|
Donggyu Kim
|
60d90f5230
|
recover collectNodesIntoComp in Backends.scala
|
2014-09-25 06:46:50 -07:00 |
|