riscv/rocket-chip
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Author SHA1 Message Date
Huy Vo 09247c0e0b fix to sram init pins 2013-09-19 20:12:10 -07:00
Huy Vo c9813603ee Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 2013-09-19 20:11:11 -07:00
Huy Vo cc3dc1bd0f bug fix 2013-09-19 20:10:56 -07:00
Huy Vo d7d13255db chisel tag 2013-08-12 20:53:29 -07:00
Huy Vo f9d1403a92 tags 2013-08-12 20:53:17 -07:00
Huy Vo cc6631ae4d reset -> _reset 2013-08-12 20:52:55 -07:00
Huy Vo d5c9eb0f54 reset -> resetVal, getReset -> reset 2013-08-12 20:52:18 -07:00
Huy Vo 2ac3fd5306 get rid of init_node 2013-04-20 01:36:32 -07:00
Huy Vo 0d87e3bacc fixed init pin generation 2013-04-20 00:38:01 -07:00
Huy Vo f67f8829e3 new rocket + uncore tags, added uncore dependencies to Makefrag 2012-10-10 15:44:19 -07:00
Huy Vo 08ab076217 forgot to change package + using fromBits in memserdes instead of manual unpacking 2012-10-10 15:42:39 -07:00
Huy Vo 9610622ab0 moving memserdes + slowio into src 2012-10-10 12:41:11 -07:00
Huy Vo 35f213e735 Merge branch 'master' of ../rocket-clone 2012-10-10 12:39:48 -07:00
Huy Vo 24a49350cc reference chip design 2012-10-09 13:05:56 -07:00
Huy Vo 916c1019af fixed memdessert unpacking 2012-10-09 13:03:17 -07:00
Huy Vo 93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00
Huy Vo 8560ea6e40 rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags 2012-10-01 19:12:18 -07:00
Huy Vo cf8f20584e factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Huy Vo 2413763f3d henry's uncore and rocket changes for new xact types 2012-10-01 16:05:37 -07:00
Huy Vo fa8075570a move srcs into src dir, factoring out uncore consts into consts 2012-09-27 12:59:45 -07:00
Huy Vo 084a0d31c3 initial commit, all the relevant submodules 2012-09-26 17:46:17 -07:00
Huy Vo a79747a062 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo 18bc14058b INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo 166b857055 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo 0c6bade592 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo 9b3161920f moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo f2942f79f9 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo 6f2f1ba21c removing wires 2012-05-24 10:42:39 -07:00
Huy Vo 0208e9f95e removing wires 2012-05-24 10:42:39 -07:00
Huy Vo 1b733e7cf0 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo 6e32cc8b20 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-13 12:34:39 -07:00
Huy Vo 0fd777f480 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo aa099a53fa Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo e22106af3f updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00