riscv/rocket-chip
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Author SHA1 Message Date
Sagar Karandikar
ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity 2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b fix NSets calculation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674 add 2 and 4 memory channel configs 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Henry Cook
3698153535 OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank 2015-11-03 14:31:35 -08:00
Howard Mao
3e906c8620 shave off channel select bits in MultiChannel router 2015-11-02 22:39:50 -08:00
Howard Mao
baa2544651 Fix some more issues with narrower 2015-10-31 19:36:30 -07:00
Howard Mao
d844bee310 properly shift grant data when checking correctness 2015-10-31 18:58:05 -07:00
Howard Mao
644b66a3a8 selectively enable or disable uncached and cached generators 2015-10-31 17:43:25 -07:00
Howard Mao
bcc631f756 generate word-size requests in uncached generator 2015-10-31 17:43:08 -07:00
Howard Mao
812c5bcc55 make sure narrower can handle sub-block level requests correctly 2015-10-31 15:58:36 -07:00
Howard Mao
d4b8653002 fix too strict assertion in broadcast hub 2015-10-31 15:58:10 -07:00
Howard Mao
c1f42ce3d4 add an L1 cache request generator 2015-10-30 12:49:57 -07:00
Colin Schmidt
032bdd0601 Merge pull request #24 from ucb-bar/regression-master 
Add a "--master" flag to the regression script
 2015-10-29 14:15:44 -07:00
Palmer Dabbelt
3d2a4ffdd6 Add a "--master" flag to the regression script 
I want to be able to test the master of riscv-gnu-toolchain against the current
RTL as part of the buildbot.  This flag takes a list of repositories (by their
submodule path) and updates those to the current master, which facilitates that
check.
 2015-10-29 14:11:26 -07:00
Howard Mao
3103fa8da2 rename tl to mem in generator 2015-10-27 17:14:56 -07:00
Howard Mao
c10870a87c make sure ID width requirement in TL -> NASTI converter is correct 2015-10-27 13:25:29 -07:00
Howard Mao
aeb9c86459 use the uncached port instead of the cached port 2015-10-26 23:09:36 -07:00
Howard Mao
b22088d934 make sure data checked is same as data sent 2015-10-26 21:55:04 -07:00
Howard Mao
2b252bc6ff first commit 2015-10-26 21:43:50 -07:00
Colin Schmidt
86d67051b2 Merge commit 'e31be75' into rocc-fpu-port 2015-10-26 16:29:51 -07:00
Howard Mao
eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Howard Mao
096dbb3c2d get rid of NastiTopInterconnect 2015-10-26 14:14:53 -07:00
Howard Mao
5440d6c2ae balance MultiChannel router correctly 2015-10-26 12:23:03 -07:00
Howard Mao
9fa4541916 get rid of unused full signal in ReorderQueue 2015-10-26 12:17:25 -07:00
Howard Mao
3270d17ad3 add MultiChannel routing to Nasti interconnect generator 2015-10-26 12:16:17 -07:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Yunsup Lee
c7235fecb5 further state optimization in CSRfile when not UseVM 2015-10-25 10:23:46 -07:00
Howard Mao
c3a7dcf0ab fix missing cde library dependencies in submodules 2015-10-23 15:05:19 -07:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Colin Schmidt
652fb393a3 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-22 16:38:28 -07:00
Howard Mao
6403f27fbe fix bug in ReorderQueue breaking TileLink Unwrapper 2015-10-22 15:52:55 -07:00
Jim Lawson
0c587704a7 Add ability to generate libraryDependency on cde. 2015-10-22 11:37:20 -07:00
Jim Lawson
4c2b0a9032 Add ability to generate libraryDependency on cde. 2015-10-22 09:57:02 -07:00
Jim Lawson
8fe4917d8e Add ability to generate libraryDependency on cde. 2015-10-22 09:52:26 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Henry Cook
47bc193c16 added CDE library as submodule 2015-10-21 18:24:16 -07:00
Henry Cook
4f8468b60f depend on external cde library 2015-10-21 18:19:23 -07:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Henry Cook
9c3cd8f9fe depend on external cde library 2015-10-21 18:16:03 -07:00
Colin Schmidt
942f6a7d7f Merge commit 'd1eae61970f864afe4fde8ca7f75380c70c4658f' into rocc-fpu-port 2015-10-21 17:18:20 -07:00
Howard Mao
21f342ad42 fix typo causing L2 cache configuration to fail 2015-10-21 13:37:33 -07:00
Colin Schmidt
97f29b1618 Merge remote-tracking branch 'origin/master' into rocc-fpu-port 2015-10-21 11:33:42 -07:00
Howard Mao
02d113b39f outerDataBits / innerDataBits should be per beat, not per block 2015-10-21 11:31:13 -07:00
Howard Mao
d5a75fd113 accidentally committed some code I didn't mean to in Rocket 2015-10-21 09:21:54 -07:00
Howard Mao
0b7c828b5d go back to using standard LockingArbiter 2015-10-21 09:15:51 -07:00