Andrew Waterman
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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Huy Vo
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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Andrew Waterman
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a2f6d01c1b
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add programmable coreid register
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2012-05-09 03:09:22 -07:00 |
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Andrew Waterman
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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Andrew Waterman
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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3a487ac89b
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improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
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Andrew Waterman
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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Yunsup Lee
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8c50c81b81
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drop vec_irq_aux pcr register, now everything goes through badvaddr
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2012-03-17 14:03:57 -07:00 |
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Yunsup Lee
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b19d783fbd
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add vector irq handler
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2012-03-14 14:15:28 -07:00 |
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Yunsup Lee
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040d62f372
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refactored vector exception handling interface
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2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
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b100544b25
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datapath to read out vector state
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2012-03-13 23:45:34 -07:00 |
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Yunsup Lee
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a1b30282dd
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major refactoring on vector exception interface
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2012-03-09 01:09:22 -08:00 |
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Yunsup Lee
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d4ec7ff4d9
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refined vector exception interface
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2012-03-03 16:11:54 -08:00 |
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Yunsup Lee
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1054cec087
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add vec countq interface
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2012-03-02 00:43:32 -08:00 |
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Huy Vo
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5b0f7ccf68
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updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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2012-02-26 17:24:08 -08:00 |
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Yunsup Lee
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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Yunsup Lee
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946e0c6e4e
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add vector exception infrastructure
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2012-02-25 16:37:56 -08:00 |
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Andrew Waterman
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
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Andrew Waterman
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1b5e39e7fc
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fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
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2012-02-15 21:36:08 -08:00 |
|
Andrew Waterman
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
|
Yunsup Lee
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f47d888feb
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vvcfgivl and vsetvl works
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2012-02-09 02:35:21 -08:00 |
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Andrew Waterman
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128ec567ed
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make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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Yunsup Lee
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fcc8081c4d
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hook up the vector command queue
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2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
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b3f6f9a5fd
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fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
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2012-02-08 15:05:28 -08:00 |
|
Andrew Waterman
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5403d069e9
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add fp loads/stores
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2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
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41855a6d47
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fix missing "otherwise" in PCR file
this fixes timer interrupts for VLSI backend.
|
2012-01-26 19:33:55 -08:00 |
|
Andrew Waterman
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f1c355e3cd
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check pc/effective address sign extension
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2012-01-24 00:15:17 -08:00 |
|
Andrew Waterman
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a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
|
Henry Cook
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1d76255dc1
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new chisel version jar and find and replace INPUT and OUTPUT
|
2012-01-18 14:39:57 -08:00 |
|
Andrew Waterman
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0369b05deb
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move replays to writeback stage
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2012-01-17 21:12:31 -08:00 |
|
Andrew Waterman
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1c8f496811
|
fix fpga build
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2012-01-13 20:04:11 -08:00 |
|
Andrew Waterman
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142dfc6e07
|
made tohost/fromhost 64 bits wide
|
2012-01-03 15:09:08 -08:00 |
|
Andrew Waterman
|
3045b33460
|
remove second RF write port
load miss writebacks are treated like mul/div now.
|
2012-01-02 02:51:30 -08:00 |
|
Andrew Waterman
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2f8fcebea0
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remove datapath register resets resets
|
2012-01-01 16:09:40 -08:00 |
|
Rimas Avizienis
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da2fdf4f85
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fixed console i/o
|
2011-11-30 22:51:59 -08:00 |
|
Rimas Avizienis
|
c42d8149b7
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
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2011-11-17 23:50:45 -08:00 |
|
Rimas Avizienis
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db87924fbf
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made eret instruction take an illegal inst exception when ET is set
|
2011-11-14 14:35:10 -08:00 |
|
Rimas Avizienis
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cd6e463320
|
added ei and di instructions
|
2011-11-14 13:48:49 -08:00 |
|
Rimas Avizienis
|
b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
890bfa7c48
|
added IPIs and timer interrupts
|
2011-11-14 03:24:02 -08:00 |
|
Rimas Avizienis
|
5b29765917
|
synced up with supervisor mode state in latest ISA simulator
|
2011-11-14 01:37:20 -08:00 |
|
Rimas Avizienis
|
345f950eff
|
added timer interrupt support
|
2011-11-13 00:27:57 -08:00 |
|
Rimas Avizienis
|
e4fa94aa27
|
checkpoint
|
2011-11-10 17:41:22 -08:00 |
|
Rimas Avizienis
|
f86d5b1334
|
cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
|
2011-11-10 11:26:13 -08:00 |
|
Rimas Avizienis
|
4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
|
2011-11-10 03:38:59 -08:00 |
|
Rimas Avizienis
|
603ede8bfe
|
access faults now write badvaddr PCR register with faulting address
|
2011-11-10 02:46:09 -08:00 |
|
Rimas Avizienis
|
36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
|
2011-11-10 02:26:26 -08:00 |
|
Rimas Avizienis
|
c29d2821b4
|
cleanup, fixes, initial commit for dtlb.scala
|
2011-11-09 21:54:11 -08:00 |
|
Rimas Avizienis
|
e96430d862
|
integrating ITLB & PTW
|
2011-11-09 14:52:17 -08:00 |
|
Rimas Avizienis
|
c06e2d16e4
|
initial commit of rocket chisel project, riscv assembly tests and benchmarks
|
2011-10-25 23:02:47 -07:00 |
|