192 lines
7.2 KiB
Scala
192 lines
7.2 KiB
Scala
package Top
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{
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import Chisel._;
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import Node._;
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import Constants._;
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class ioDpathBTB extends Bundle()
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{
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val current_pc4 = UFix(VADDR_BITS, 'input);
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val hit = Bool('output);
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val target = UFix(VADDR_BITS, 'output);
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val wen = Bool('input);
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val correct_pc4 = UFix(VADDR_BITS, 'input);
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val correct_target = UFix(VADDR_BITS, 'input);
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}
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class rocketDpathBTB extends Component
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{
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override val io = new ioDpathBTB();
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val rst_lwlr_pf = Mem(4, io.wen, io.correct_pc4(3, 2), UFix(1, 1), resetVal = UFix(0, 1));
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val lwlr_pf = Mem(4, io.wen, io.correct_pc4(3, 2),
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Cat(io.correct_pc4(VADDR_BITS-1,4), io.correct_target(VADDR_BITS-1,2)), resetVal = UFix(0, 1));
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val is_val = rst_lwlr_pf(io.current_pc4(3, 2));
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val tag_target = lwlr_pf(io.current_pc4(3, 2));
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io.hit := (is_val & (tag_target(2*VADDR_BITS-7,VADDR_BITS-2) === io.current_pc4(VADDR_BITS-1, 4))).toBool;
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io.target := Cat(tag_target(VADDR_BITS-3, 0), Bits(0,2)).toUFix;
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}
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class ioDpathPCR extends Bundle()
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{
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val host = new ioHost(List("from", "from_wen", "to"));
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val debug = new ioDebug(List("error_mode", "log_control"));
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val r = new ioReadPort();
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val w = new ioWritePort();
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val status = Bits(17, 'output);
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val ptbr = UFix(PADDR_BITS, 'output);
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val evec = UFix(VADDR_BITS, 'output);
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val exception = Bool('input);
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val cause = UFix(5, 'input);
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val pc = UFix(VADDR_BITS, 'input);
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val eret = Bool('input);
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}
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class rocketDpathPCR extends Component
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{
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val io = new ioDpathPCR();
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val w = 32;
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val reg_epc = Reg(resetVal = UFix(0, VADDR_BITS));
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val reg_badvaddr = Reg(resetVal = UFix(0, VADDR_BITS));
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val reg_ebase = Reg(resetVal = UFix(0, VADDR_BITS));
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val reg_count = Reg(resetVal = Bits(0, w));
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val reg_compare = Reg(resetVal = Bits(0, w));
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val reg_cause = Reg(resetVal = Bits(0, 5));
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val reg_tohost = Reg(resetVal = Bits(0, w));
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val reg_fromhost = Reg(resetVal = Bits(0, w));
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val reg_k0 = Reg(resetVal = Bits(0, 2*w));
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val reg_k1 = Reg(resetVal = Bits(0, 2*w));
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val reg_ptbr = Reg(resetVal = UFix(0, PADDR_BITS));
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val reg_error_mode = Reg(resetVal = Bool(false));
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val reg_log_control = Reg(resetVal = Bool(false));
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val reg_status_vm = Reg(resetVal = Bool(false));
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val reg_status_im = Reg(resetVal = Bits(0,8));
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val reg_status_sx = Reg(resetVal = Bool(true));
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val reg_status_ux = Reg(resetVal = Bool(true));
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val reg_status_ef = Reg(resetVal = Bool(false));
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val reg_status_ev = Reg(resetVal = Bool(false));
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val reg_status_s = Reg(resetVal = Bool(true));
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val reg_status_ps = Reg(resetVal = Bool(false));
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val reg_status_et = Reg(resetVal = Bool(false));
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val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, Bits(0,1), reg_status_ev, reg_status_ef, reg_status_et);
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val rdata = Wire() { Bits() };
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io.status := Cat(reg_status_vm, reg_status_im, reg_status);
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io.evec := reg_ebase;
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io.ptbr := reg_ptbr;
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io.host.to := Mux(io.host.from_wen, Bits(0, w), reg_tohost);
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io.debug.error_mode := reg_error_mode;
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io.debug.log_control := reg_log_control;
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io.r.data := rdata;
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when (io.host.from_wen) {
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reg_tohost <== Bits(0, w);
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reg_fromhost <== io.host.from;
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}
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otherwise {
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when (!io.exception && io.w.en && (io.w.addr === PCR_TOHOST)) {
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reg_tohost <== io.w.data(w-1, 0);
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reg_fromhost <== Bits(0, w);
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}
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}
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when (io.exception && !reg_status_et) {
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reg_error_mode <== Bool(true);
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}
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when (io.exception && reg_status_et) {
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reg_status_s <== Bool(true);
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reg_status_ps <== reg_status_s;
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reg_status_et <== Bool(false);
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reg_epc <== io.pc;
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reg_cause <== io.cause;
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}
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when (!io.exception && io.eret) {
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reg_status_s <== reg_status_ps;
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reg_status_et <== Bool(true);
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}
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when (!io.exception && !io.eret && io.w.en) {
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when (io.w.addr === PCR_STATUS) {
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reg_status_vm <== io.w.data(16).toBool;
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reg_status_im <== io.w.data(15,8);
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reg_status_sx <== io.w.data(7).toBool;
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reg_status_ux <== io.w.data(6).toBool;
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reg_status_s <== io.w.data(5).toBool;
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reg_status_ps <== io.w.data(4).toBool;
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reg_status_ev <== HAVE_VEC && io.w.data(2).toBool;
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reg_status_ef <== HAVE_FPU && io.w.data(1).toBool;
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reg_status_et <== io.w.data(0).toBool;
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}
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when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS-1,0).toUFix; }
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when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS-1,0).toUFix; }
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when (io.w.addr === PCR_EVEC) { reg_ebase <== io.w.data(VADDR_BITS-1,0).toUFix; }
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when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(w-1,0); }
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when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(w-1,0); }
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when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); }
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when (io.w.addr === PCR_LOG) { reg_log_control <== io.w.data(0).toBool; }
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when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data(w-1,0); }
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when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
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when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; }
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when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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}
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when (!io.r.en) { rdata <== Bits(0,2*w); }
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switch (io.r.addr) {
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is (PCR_STATUS) { rdata <== Cat(Bits(0,w+15), reg_status_vm, reg_status_im, reg_status); }
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is (PCR_EPC) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_epc(VADDR_BITS-1)), reg_epc); }
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is (PCR_BADVADDR) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_badvaddr(VADDR_BITS-1)), reg_badvaddr); }
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is (PCR_EVEC) { rdata <== Cat(Fill(2*w-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
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is (PCR_COUNT) { rdata <== Cat(Fill(w, reg_count(w-1)), reg_count); }
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is (PCR_COMPARE) { rdata <== Cat(Fill(w, reg_compare(w-1)), reg_compare); }
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is (PCR_CAUSE) { rdata <== Cat(Bits(0,w+27), reg_cause); }
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is (PCR_MEMSIZE) { rdata <== MEMSIZE; }
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is (PCR_LOG) { rdata <== Cat(Bits(0,63), reg_log_control); }
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is (PCR_FROMHOST) { rdata <== Cat(Fill(w, reg_fromhost(w-1)), reg_fromhost); }
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is (PCR_TOHOST) { rdata <== Cat(Fill(w, reg_tohost(w-1)), reg_tohost); }
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is (PCR_K0) { rdata <== reg_k0; }
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is (PCR_K1) { rdata <== reg_k1; }
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is (PCR_PTBR) { rdata <== Cat(Bits(0,2*w-PADDR_BITS), reg_ptbr); }
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otherwise { rdata <== Bits(0,2*w); }
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}
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}
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class ioReadPort extends Bundle()
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{
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val addr = UFix(5, 'input);
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val en = Bool('input);
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val data = Bits(64, 'output);
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}
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class ioWritePort extends Bundle()
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{
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val addr = UFix(5, 'input);
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val en = Bool('input);
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val data = Bits(64, 'input);
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}
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class ioRegfile extends Bundle()
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{
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val r0 = new ioReadPort();
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val r1 = new ioReadPort();
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val w0 = new ioWritePort();
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val w1 = new ioWritePort();
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}
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class rocketDpathRegfile extends Component
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{
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override val io = new ioRegfile();
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val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);
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regfile.write(io.w1.en && (io.w1.addr != UFix(0,5)), io.w1.addr, io.w1.data);
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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}
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